Company patents
Kepler Computing Inc.
Kepler Computing Inc. surprisingly shows a broad decline across its core semiconductor patent categories, with significant year-over-year drops in 2025 for Memory Devices (Structural) (-40.4%), Memory & Storage (Static) (-14.8%), and Pulse / Digital Logic Circuits (-19.0%), indicating a shifting priority away from these foundational areas. While Computer Hardware Architecture saw a strong 55.6% growth in 2024, its subsequent decline in 2025 (-21.4%) and the partial data for 2026 suggest a broader re-evaluation of its patenting efforts, with only 4 patents so far in 2026.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
280 US filings (since 2023) · 12 categories · 17 themes
Design and implementation of non-traditional logic gates or memory elements, often leveraging new materials or device physics to achieve multi-functionality, adaptive thresholds, or higher density.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.
Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.
Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.
Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.
Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Patents
Showing 11-20 of 368