Kioxia Corporation

A method for manufacturing a semiconductor device includes: forming a structural body on a substrate, the structural body comprising a recess with respect to a first surface of the structural body; providing a first portion of a plurality of insulating particles inside the recess and below the first surface; annealing the first portion of the insulating particles inside the recess; and filling gaps between the first portion of the insulating particles with a liquid insulator.

A semiconductor device includes a first electrode, a second electrode provided above the first electrode in a first direction perpendicular to a surface of the first electrode, an oxide semiconductor having a first end in contact with the first electrode and a second end in contact with the second electrode and extending in the first direction, a gate insulating film surrounding a side surface of the oxide semiconductor, and a gate electrode surrounding a side surface of the gate insulating film. The gate electrode includes a recess provided on a surface facing the oxide semiconductor.

A semiconductor device of embodiments includes a first electrode, a second electrode, an oxide semiconductor layer between the first electrode and the second electrode, a gate electrode, a first insulating layer, a second insulating layer, and a gate insulating layer. Assuming that the thickness of the gate insulating layer between the first insulating layer and the oxide semiconductor layer is a first thickness, the thickness of the gate insulating layer between the second insulating layer and the oxide semiconductor layer is a second thickness, the thickness of the gate insulating layer between a first end of the gate electrode is a third thickness, and the thickness of the gate insulating layer between a second end of the gate electrode and the oxide semiconductor layer is a fourth thickness, the second thickness is larger than the first thickness or the fourth thickness is larger than the third thickness.

A semiconductor memory device includes first and second memory cell arrays, a first sense amplifier unit by which data is read from first and second memory cells of the first and second memory cell arrays, respectively, and a first switch circuit configured to switch between electrically connecting the first memory cells to the first sense amplifier unit, and electrically connecting the second memory cells to the first sense amplifier unit. The first memory cell array and the first sense amplifier unit overlap each other in a vertical direction; the second memory cell array is shifted in a horizontal direction with respect to the first memory cell array and the first sense amplifier unit; and the first switch circuit overlaps a region between the first and second memory cell arrays in the vertical direction or overlaps the first memory cell array in the vertical direction.

In general, according to one embodiment, a semiconductor memory device includes: first, plurality of second, third, and plurality of fourth interconnect layers which are stacked in this order in a first direction wherein the second and fourth interconnect layers include a plurality of first and second terrace portions, respectively; first and second memory pillars which extend in the first direction, pass through the second and fourth interconnect layers, respectively, and are in contact with the first and third interconnect layers, respectively; first and third contacts which extends in the first direction and are in contact with one of the first and second terrace portions, respectively; and a second contact which extends in the first direction above the first contact, and passes through the fourth interconnect layers.

A semiconductor storage device includes a stack, a columnar body, and a second conductive layer. The stack includes a plurality of first conductive layers and a plurality of insulating layers. In the stack, the plurality of first conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The second conductive layer is connected to the columnar body. The columnar body includes an insulating core, a memory film, and a semiconductor channel. The memory film is provided between the plurality of first conductive layers and the insulating core. The semiconductor channel is provided between the insulating core and the memory film. An upper surface of the insulating core is located lower than an upper end of the columnar body. The second conductive layer has a main body portion and a protrusion. The protrusion protrudes from the main body portion toward the upper surface of the insulating core, and extends in the first direction within the columnar body. The protrusion is in contact with the semiconductor channel on a bottom surface or a side surface of the protrusion.

A semiconductor memory device includes: a stacked body including conductive and insulating layers that are alternately stacked in a first direction; memory pillars extending in the first direction in the stacked body; and a structure body segmenting the memory pillars and extending in the first direction in the stacked body. The structure body includes a crystalline conductor extending in the first direction in the stacked body, a first insulating film between the stacked body and the crystalline conductor, a crystalline semiconductor film between the crystalline conductor and the first insulating film, and a second insulating film between the crystalline semiconductor film and a side surface of the crystalline conductor. The crystalline conductor includes a first crystal region in contact with the crystalline semiconductor film and containing germanium, and a second crystal region on the first crystal region and in contact with the second insulating film in a second direction.

According to one embodiment, a memory includes: a first transistor including: a first semiconductor between the substrate and the bit line; and a first gate facing a side of the first semiconductor; a first memory element between the first transistor and the substrate; a first word line including a first conductor coupled to the first gate; a second transistor including: a second semiconductor between the substrate and the bit line; and a second gate facing a side of the second semiconductor; a second memory element between the second transistor and the substrate; and a second word line being adjacent to the first word line in a first direction and including a second conductor coupled to the second gate. The second semiconductor is adjacent to the first semiconductor in a second direction intersecting the first direction.

According to one embodiment, a semiconductor memory device includes a first word line, a second word line, a first memory cell connected to the first word line, a second memory cell connected to the second word line, and a control circuit configured to perform a data write operation to the first memory cell and the second memory cell. In the write operation, a plurality of program loops each including a program operation and a verify operation are sequentially executed. In the verify operation for a first memory cell, the control circuit applies a second voltage to a first word line in a case of applying a first voltage to a second word line, and then applies a third voltage according to a write state to the first word line to change a voltage level of the second voltage according to the progress of the program loops.

A semiconductor memory device includes a first semiconductor layer, a first gate electrode layer, a second gate electrode layer including a first region and a second region that is separated from the first region, the first semiconductor layer being provided between the first region and the second region, a third gate electrode layer that is provided between the first gate electrode layer and the second gate electrode layer, and includes a third region and a fourth region that is separated from the third region, the first semiconductor layer being provided between the third region and the fourth region, a first charge storage layer provided between the first semiconductor layer and the first gate electrode layer, and having an annular shape, a second charge storage layer provided between the first semiconductor layer and the second region, and having a horseshoe shape, and a third charge storage layer provided between the first semiconductor layer and the fourth region, and having a horseshoe shape. A first distance from an end of the second region to an end of the second charge storage layer is greater than a second distance from an end of the fourth region to an end of the third charge storage layer.