LAPIS TECHNOLOGY CO., LTD.

A clock error detection circuit which includes a cycle signal generation circuit that generates a cycle signal that reverses a level thereof at a start of each one cycle of a subject clock signal, a delay circuit that delays the cycle signal by a time shorter or a time longer than a prescribed cycle for the subject clock signal to output a delayed signal of the cycle signal, a holding circuit that holds a level of the delayed signal at the start of each one cycle of the subject clock signal to generate a hold signal, and a determination circuit that determines whether the level of the cycle signal matches the level of the hold signal to generate a result of the determination.

A flash memory is a memory element that stores a trimming code for adjusting a resistance value of a trimming resistor so that an oscillation frequency of an output clock signal generated by a CR oscillator circuit becomes a preset frequency. The CR oscillator circuit generates the output clock signal having a frequency based on a time constant determined by a resistance value of the trimming resistor being a resistive element, and a capacitance value of a capacitive element. An up-down counter is a counter circuit that, in synchronization with the output clock signal generated by the CR oscillator circuit, increases or decreases the trimming code stored in the flash memory, and outputs the trimming code as a trimming code for adjusting the resistance value of the trimming resistor.

A multi-die module includes: a first semiconductor die having an internal line, an external electrode, and multiple internal electrodes and including a first control circuit that control a DC-DC converter; a second semiconductor die having multiple internal electrodes and including a second control circuit that controls a linear regulator; and a package that supports the first and second semiconductor dies. The second control circuit includes a voltage comparison circuit having a feedback input, a reference input, and a comparison output. In each of the first and second semiconductor dies, the multiple internal electrodes includes a first internal electrode. The feedback input of the voltage comparison circuit is connected to the first internal electrode of the second semiconductor die, which is connected to the first internal electrode of the first semiconductor die. The internal line connects the first internal electrode of the first semiconductor die to the external electrode.

A display device includes a video data signal output portion including a gamma setting data generation portion that generates gamma setting data, which is setting information for gamma correction corresponding to at least one partial area of a display screen of the display panel, based on the video data. The source driver includes: a gamma curve generation portion, configured to receive the gamma setting data and generate a local gamma correction curve, which is a gamma correction curve corresponding to the at least one partial area, based on the gamma setting data; a decoder portion, configured to perform gamma correction of gradation voltages corresponding to the plurality of pixel data fragments for each of the at least one partial area based on the local gamma correction curve; and an output portion, configured to output the pixel driving voltage based on the gradation voltages that have undergone the gamma correction.

A digital-to-analog conversion device includes a Gray code conversion circuit receiving a series of digital data pieces including binary codes, and generating Gray code data pieces obtained by respectively converting the digital data pieces into Gray codes; a decoder receiving the Gray code data pieces and a plurality of reference voltages having different voltage values, selecting two reference voltages including an overlap from the plurality of reference voltages based on the Gray code data pieces, and outputting the two reference voltages as a first selection voltage and a second selection voltage, respectively; and an amplifier circuit including first and second input terminals that respectively receive the first selection voltage and the second selection voltage, and generating an output voltage by amplifying a voltage obtained by interpolating the first selection voltage and the second selection voltage by a weighting ratio assigned to the first and second input terminals.

An output amplifier circuit, and a display driver and a display device including the output amplifier circuit. The output amplifier circuit includes: first to nth amplifiers which receive first to nth input voltages and generate first to nth output voltages by amplifying the respective first to nth input voltages; first to Kth bias circuits which are provided corresponding to each of first to Kth amplifier groups formed by grouping the first to nth amplifiers into K groups, and each generates a bias voltage for setting a current value of an operating current of the amplifiers; first to Kth wirings which supply the bias voltage generated by each of the first to Kth bias circuits to the first to Kth amplifier groups respectively; and a switch circuit which, when in an ON state, connects one wiring among the first to Kth wirings with another wiring different from the one wiring.

A charge pump circuit includes: first and second capacitors; a first switch element group turned on and off by a first clock signal and connecting a first voltage supply line and the first capacitor when turned on; a second switch element group turned on and off by the first clock signal and connecting a second voltage supply line and the second capacitor when turned on; and a third switch element group turned on and off by a second clock signal and connecting a voltage output line and the first and second capacitors when turned on. A control circuit controls a timing of a signal change of a first enable signal so that the signal levels of the first and second clock signals are fixed when the first and second switch element groups change from off to on, in response to stopping oscillating the first and second clock signals.

A level shifter includes: an input stage circuit receiving a relatively low level input signal, and an output stage circuit converting the input signal into a relatively high level signal and outputting the signal. The output stage circuit includes: first and second transistors, to which complementary signals generated according to the input signal are respectively input; a first switch circuit, having a main path connected with the first transistor, entering an ON-state with the second transistor entering the ON-state, and entering an OFF-state with the second transistor entering the OFF-state; and a second switch circuit, having a main path connected with the second transistor, entering the ON-state with the first transistor entering the ON-state, and entering the OFF-state with the first transistor entering the OFF-state. Regarding ON-resistance, the first switch circuit is greater than the first transistor, and the second switch circuit is greater than the second transistor.

An abnormal condition detection system includes a voice abnormality detector that includes a normal time model generator for generating a model of normal time voice data of a person riding in a vehicle as a normal time model based on voice data including voice of the person, and detects an abnormality in the voice based on a current voice data of the person and the normal time model; a vehicle body abnormality detector that detects an abnormality in a vehicle body of the vehicle based on acceleration data of the vehicle; and an abnormal condition determiner that determines whether or not the vehicle is in an abnormal condition based on a detection result of the voice abnormality detector and a detection result of the vehicle body abnormality detector.

A control device including: a processor, the processor being configured to: acquire write data; store the write data as first write data in a first region of a non-volatile storage section with an error detection code attached; store the first write data as second write data in a second region of a non-rewritable storage section; and store the second write data as third write data in a third region of the non-volatile storage section.