Lattice Semiconductor Corporation

Various techniques are provided to implement information leakage mitigation associated with data communications. In one example, a method includes receiving a bitstream including a plurality of bits. The method further includes, for each bit of the plurality of bits, transitioning between two states of a plurality of states in response to the bit; inverting a differential pair of data signals associated with the bit in response to the transitioning to obtain differentially transitioned data signals; maintaining a third data signal associated with the bit in response to the transitioning; and transmitting each data signal of the differentially transitioned data signals and the third data signal over a respective wire. Related systems and devices are provided.

A system, method, and computer program product for performing attestation by a baseboard management controller (BMC) of target devices are provided. A data center secure control module (DC-SCM) coupled to BMC includes a PLD with an arbiter that communicates using LTPI IP over I2C with the HPM. The BMC issues MCPT requests for attestation information to target devices. The arbiter at the DC-SCM establishes a two-way communication mode over the LTPI IP with the HPM to transfer the requests to the HPM on a primary LTPI I2C channel. A PLD with an arbiter at HPM routes the requests to target devices using virtual I2C nodes. The target devices issue responses with the attestation information. The responses are routed to the arbiter of the HPM, that uses the virtual I2C nodes to route the responses over a secondary LTPI I2C channel to the DC-SCM. The DC-SCM routes the responses to the BMC.

Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). A method includes configuring a programmable logic device (PLD) having a fabric of programmable logic blocks arranged in a plurality of regions; routing data carry chains in a first direction across the fabric to each of the plurality of regions; placing global clock circuitry at a first edge of the PLD; and routing the global clock to a corresponding first edge of each region via a global clock trunk and a plurality of clock branches, the global clock trunk propagating the global clock signal across the fabric and in each region, in the same direction as the data carry chains.

Various techniques are provided to configure serializer/deserializer (SerDes) lanes in one or more SerDes quads into configurable groups using a bonded link. The configuration registers may configure the SerDes lanes into the configurable groups. A lane bonding control module in each SerDes quad may link the signals, including control signals, that travel within each configurable group. To synchronize the control signals, the lane bonding control module may include one or more flops that introduce a fixed time delay for control signals that travel between SerDes quads, and pipe stage match modules that introduce a variable time delay to match the fixed time delay caused by the flops. Once synchronized, the control signals arrive at different SerDes lanes in the configurable group at the same clock cycle.

A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input/output interface and executes the one or more layers.

Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). In one example, a method comprises configuring an intellectual property (IP) block of the PLD to receive a first clock signal and a first data signal at a first component of the IP block, determining a delay associated with the first clock signal between a first input and the first component, configuring a programmable logic cell (PLC) to receive a second clock signal and output the first data signal to the IP block, determining a delay period to synchronize the first clock signal and the first data signal at the first component of the IP block, and configuring an adjustable delay element to apply the delay period to the second clock signal to synchronize the first clock signal and the first data signal at the first component of the IP block.

Various techniques are provided for implementing one or more multi-mode look-up tables (LUTs) in programmable logic devices (PLDs). In one example, a PLD includes a multi-mode LUT. The comprising: a plurality of input nodes configured to receive a plurality of input signals; wherein the multi-mode LUT is configurable to selectively operate in a first mode as a single LUT or in a second mode as dual LUTs and generate a plurality of output signals in accordance with one or more logic functions in response to the input signals; and a plurality of output nodes configured to provide the plurality of output signals simultaneously to routing resources of the PLD.

A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

Various techniques are provided for managing power modes (e.g., also referred to as power states) in peripheral devices connected to host devices. In one example, a method includes receiving, by an intermediate device communicatively connected between a host device and a peripheral device, a notification that the host device will transition from a high power mode to a reduced power mode. The method also includes receiving, by the intermediate device from the peripheral device, context data associated with an operational state of the peripheral device. The method also includes storing, by the intermediate device, the context data, and power gating the peripheral device by the intermediate device while the host device remains at least partially turned on in the reduced power mode. Additional embodiments are provided to restore the operational state of the peripheral device using the stored context data. Additional systems, devices, and methods are also provided.

Various techniques are provided to implement dual power supplied memory cells and deterministic reset thereof for programmable logic devices. In one example, a programmable logic device (PLD) includes a configuration memory including an array of memory cells arranged in rows and columns. The PLD further includes a power supply circuit coupled to the configuration memory and configured to selectively couple, based on a reset control signal, a power supply to a first power supply line coupled to the array of memory cells. The array of memory cells is reset if the power supply is coupled to the first power supply line. The power supply circuit is further configured to provide power on a second power supply line to the array of memory cells. Related methods and devices are provided.