Lightmatter, Inc.

Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.

Hybrid analog-digital processing systems are described. An example of a hybrid analog-digital processing system includes photonic accelerator configured to perform matrix-vector multiplication using light. The photonic accelerator exhibits a frequency response having a first bandwidth (e.g., less than 3 GHz). The hybrid analog-digital processing system further includes a plurality of analog-to-digital converters (ADCs) coupled to the photonic accelerator, and a plurality of digital equalizers coupled to the plurality of ADCs, wherein the digital equalizers are configured to set a frequency response of the hybrid analog-digital processing system to a second bandwidth greater than the first bandwidth.

A photonic processor uses light signals and a residue number system (RNS) to perform calculations. The processor sums two or more values by shifting the phase of a light signal with phase shifters and reading out the summed phase with a coherent detector. Because phase winds back every 2π radians, the photonic processor performs addition modulo 2π. A photonic processor may use the summation of phases to perform dot products and correct erroneous residues. A photonic processor may use the RNS in combination with a positional number system (PNS) to extend the numerical range of the photonic processor, which may be used to accelerate homomorphic encryption (HE)-based deep learning.

Described herein are photonic communication platforms and related packages. In one example, a photonic package includes a substrate carrier having a recess formed through the top surface of the substrate carrier. The substrate carrier may be made of a ceramic laminate. A photonic substrate including a plurality of photonic modules is disposed in the recess. The photonic modules may be patterned using a common photomask, and as a result, may share a same layer pattern. A plurality of electronic dies may be positioned on top of respective photonic modules. The photonic modules enable communication among the dies in the optical domain. Power delivery substrates may be used to convey electric power from the substrate carrier to the electronic dies and to the photonic substrate. Power delivery substrates may be implemented, for example, using bridge dies or interposers (e.g., silicon or organic interposers).

Described herein are wavelength division multiplexing (WDM) transceivers configured to support fast, bidirectional communication over optical channels. An optical transceiver comprises a transmitter, a receiver, an input/output (I/O) port and an optical interleaver. The transmitter comprises a first bus waveguide and a plurality of optical modulators coupled to the first bus waveguide, each of the optical modulators being resonant at a respective wavelengths in a first wavelength set. The receiver comprises a second bus waveguide and a plurality of optical filters coupled to the second bus waveguide, each of the optical filters being resonant at a respective wavelength in a second wavelength set. The (I/O) port is coupled to an optical channel. The optical interleaver is configured to selectively couple light having wavelengths in the first wavelength set from the first waveguide bus to the I/O port, and selectively couple light having wavelengths in the second wavelength set from the I/O port to the second bus waveguide.

Systems and methods for performing signed matrix operations using a linear photonic processor are provided. The linear photonic processor is formed as an array of first amplitude modulators and second amplitude modulators, the first amplitude modulators configured to encode elements of a vector into first optical signals and the second amplitude modulators configured to encode a product between the vector elements and matrix elements into second optical signals. An apparatus may be used to implement a signed value of an output of the linear processor. The linear photonic processor may be configured to perform matrix-vector and/or matrix-matrix operations.

Described herein are compact, power efficient photonic processors deigned to handle general matrix-matrix (GEMM) operations. A photonic processor may comprise a controller, an optical interferometer, a plurality of signal drivers, and an optical receiver. The controller is configured to obtain a vector of input values and a matrix of parameters. The optical interferometer comprises an output and a plurality of optical phase shifters. Each signal driver of the plurality of signal drivers is configured to control a respective phase shifter to phase shift light traveling in the optical interferometer based on i) a polarity set by a respective parameter of the matrix, and ii) an amount set by a respective input value of the vector. The optical receiver is coupled to the output of the optical interferometer.

Systems and methods for performing matrix operations using a photonic processor are provided. The photonic processor includes encoders configured to encode a numerical value into an optical signal and optical multiplication devices configured to output an electrical signal proportional to a product of one or more encoded values. The optical multiplication devices include a first input waveguide, a second input waveguide, a coupler circuit coupled to the first input waveguide and the second input waveguide, a first detector and a second detector coupled to the coupler circuit, and a circuit coupled to the first detector and second detector and configured to output a current that is proportional to a product of a first input value and a second input value.

Aspects of the present application relate to an optical phase shifter including a first waveguide defined in a first semiconductor layer, the first waveguide comprising a single-mode portion, a multi-mode portion, and a tapered portion coupling the single-mode portion to the multi-mode portion. A second waveguide is defined in a second semiconductor layer, the second waveguide having a tapered portion and a tip, wherein the tapered portion of the second waveguide overlaps with the tapered portion of the first waveguide. For tuning the phase change, a first electrically resistive path, defined at least partially in the first semiconductor layer, is included. The first electrically resistive path intersects the multi-mode portion of the first waveguide.

Described herein are packages in which photonic chiplets are disposed in recesses defined on an underlying substrate. Positioning chiplets in this way allows short trace lengths between the electrical chips and the optical converters, V-groove fiber assemblies that can be attached along any direction of a photonic chiplet (north-south and/or west-east) and easy access to the electrical chips for power and signals. A package may include a substrate having a recess defined near an edge of the substrate, a photonic chiplet disposed in the recess, an electrical chiplet disposed at least in part on the photonic chiplet, and a fiber optically coupled to the photonic chiplet at the edge of the substrate. The electrical chiplet may be disposed in part on the photonic chiplet and in part on the top surface of the substrate.