Company patents
Lodestar Licensing Group LLC
Lodestar Licensing Group LLC's patent strategy shows a significant, albeit short-lived, surge in patent acquisitions across multiple computing and semiconductor categories in 2024, with categories like Memory & Storage (Static) and Computer Hardware Architecture seeing over 1200% YoY growth. This was followed by a sharp decline in patenting activity across most categories in 2025 and so far in 2026, suggesting a strategic shift away from aggressive portfolio expansion in these areas, with the exception of Industrial & Autonomous Control, which is showing an emerging focus with a 42.9% YoY growth in 2026 (partial data).
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
925 US filings (since 2023) · 12 categories · 21 themes
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.
Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Algorithms and systems for generating, optimizing, and executing trajectories for autonomous vehicles or robots to move through an environment, often involving obstacle avoidance, route validation, and goal reaching.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.
Designing user interfaces and interaction methods specifically for mobile or wearable devices, enabling control of external systems, monitoring user states, or facilitating real-world transactions.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Techniques for rendering, interacting with, and managing content within augmented or virtual reality environments, including spatial tracking, gaze interaction, and dynamic multi-application display management.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.
Applying artificial intelligence and machine learning techniques to enhance cryptographic systems, such as generating encryption models, improving zero-trust architectures, or enabling privacy-preserving computations like federated learning.
Technologies enabling the creation and management of virtual computing environments, including virtual machines and virtual desktops, with an emphasis on secure and efficient remote access, updates, and performance.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Patents
Showing 1-10 of 925