UnfoldIPThemes

Company patents

M31 TECHNOLOGY CORPORATION

M31 TECHNOLOGY CORPORATION's patent strategy is heavily concentrated in semiconductor and communications technologies, with Pulse / Digital Logic Circuits (51.1% of portfolio) and Coding & Decoding (42.2% of portfolio) being dominant areas. While Coding & Decoding saw a significant 60.0% YoY growth in 2024, the sharp decline in patent filings across nearly all categories so far in 2026, including an 87.5% drop in Pulse / Digital Logic Circuits and a 100.0% drop in Memory & Storage (Static), suggests a potential shift in R&D focus or a temporary slowdown in patenting activity.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

45 US filings (since 2023) · 8 categories · 10 themes

High-Speed Clock & Data

Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.

Pulse / Digital Logic Circuits
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26since 2023
-33.3%YoY
In-Memory Sensing & Data Path

Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.

Memory & Storage (Static)
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10since 2023
0.0%YoY
Quantum Control Circuits

Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.

Pulse / Digital Logic Circuits
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7since 2023
+33.3%YoY
Memory System Performance & Reliabilityfiltered

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Memory & Storage (Static)
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5since 2023
0.0%YoY
Power Switching & Drivers

Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.

Pulse / Digital Logic Circuits
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5since 2023
0.0%YoY
Advanced Channel Coding & Decoding

Development of encoding and decoding algorithms and apparatuses for robust data transmission and storage, focusing on techniques like LDPC, polar codes, and iterative decoding methods to minimize bit errors and improve communication reliability.

Coding & Decoding
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4since 2023
+100.0%YoY
High-Speed Data Interconnects

Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.

Computer Hardware Architecture
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4since 2023
new
Impedance Matching Networks

Circuits designed to transform the impedance of a source to match the impedance of a load, maximizing power transfer or minimizing signal reflections, often involving inductors, capacitors, and transformers.

Impedance Networks (Filters, Resonators)
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3since 2023
+100.0%YoY
Analog Sensing Interfaces

Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.

Pulse / Digital Logic Circuits
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3since 2023
n/a
High-Performance ADC/DAC Architectures

Focuses on the architectural and circuit-level innovations for Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) to improve speed, accuracy, linearity, and power efficiency. Includes specific types like SAR and Delta-Sigma, and their constituent components.

Coding & Decoding
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3since 2023
n/a

Patents

Showing 1-7 of 7

Memory System Performance & Reliability
Page 1 of 1
US 12293785 B2GRANTED
G11C11/34

Circuit module with reliable margin configuration

Filed:2024-02-16Pub:2025-05-06
Applicant:M31 TECHNOLOGY CORPORATION

A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

US 12205635 B2GRANTED
G11C11/412

Memory module with improved timing adaptivity of sensing amplification

Filed:2023-03-31Pub:2025-01-21
Applicant:M31 TECHNOLOGY CORPORATION

A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.

US 20240185912 A1APPLICATION
G11C11/4091

CIRCUIT MODULE WITH RELIABLE MARGIN CONFIGURATION

Filed:2024-02-16Pub:2024-06-06
Applicant:M31 TECHNOLOGY CORPORATION

A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

US 11935581 B2GRANTED
G11C11/34

Circuit module with reliable margin configuration

Filed:2022-05-31Pub:2024-03-19
Applicant:M31 TECHNOLOGY CORPORATION

A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

US 20230335188 A1APPLICATION
G11C11/419

MEMORY MODULE WITH IMPROVED TIMING ADAPTIVITY OF SENSING AMPLIFICATION

Filed:2023-03-31Pub:2023-10-19
Applicant:M31 TECHNOLOGY CORPORATION

A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.

US 20220399052 A1APPLICATION
G11C11/4091

CIRCUIT MODULE WITH RELIABLE MARGIN CONFIGURATION

Filed:2022-05-31Pub:2022-12-15
Applicant:M31 TECHNOLOGY CORPORATION

A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.

US 11012087 B2GRANTED
H03M9/00

Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

Filed:2019-12-02Pub:2021-05-18
Applicant:M31 TECHNOLOGY CORPORATION

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.

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