MARVELL ISRAEL (M.I.S.L) LTD.

In a memory system having a plurality of memory banks, a plurality of memory access requests having a first priority level and a plurality of memory access requests having a second priority level different are received. A set of first memory banks executes the multiple memory access requests having the first priority level during a first clock cycle. The memory system determines one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle. In response to determining the one or more second memory banks that are not executing memory access requests having the first priority level during the first clock cycle, the one or more second memory banks execute one or more memory access requests having the second priority level during the first clock cycle.

A printed circuit board (PCB) includes a plurality of stacked layers, each layer having a major plane defining a major plane of the PCB, a plurality of signal pads disposed on a signal pad layer of the PCB that is parallel to the major plane of the PCB, and a plurality of signal vias, each signal via in the plurality of signal vias having a longitudinal axis perpendicular to the major plane of the PCB, each signal via extending through the plurality of layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one signal via in the plurality of signal vias includes an added capacitive structure which, along with inductance of that via, forms a corrective filter to reduce insertion loss deviation of at least one broadband signal in that via.

A bridge receives a first memory access command from a host computer, the first memory access command including an indication of one or more blocks of memory locations in a host memory of the host computer. The bridge device stores the first memory access command in a queue of the bridge device and determines one or more virtual addresses to be used by the solid state memory for the first memory access command. The bridge generates a second memory access command that is a revised copy of the first memory access command so that the indication of the one or more blocks of memory locations in the host memory is replaced with an indication of the one or more virtual addresses. The bridge sends the second memory access command to the solid state memory while keeping the first memory access command in the queue.

A network device includes a receive processor configured to store, in a packet memory, a payload of a packet received from a communication network. The network device also includes a packet processor configured to modify one or more fields of a header of the packet to generate a modified header, perform egress classification of the packet based on the modified header, and store the modified header in the packet memory. The network device further includes a transmit processor configured to transmit the packet in accordance with the egress classification. The transmit processor is configured to, in response to a decision that the packet is to be transmitted from the network device, generate a transmit packet from the payload retrieved from the packet memory and the modified header retrieved from the packet memory and cause the transmit packet to be transmitted to a destination in the communication network.

A packet processor of a network device includes a first lookup engine that generates a first lookup key for a packet, performs a first lookup in a first database using the first lookup key, and in response to finding a match of the first lookup key in the first database, determines a plurality of processing actions to be performed for the packet. Each of multiple second lookup engines selectively performs a respective second lookup in a respective second database for the packet using a respective second lookup key, and ii) selectively determines, based on the second lookup, one or more processing actions to be performed for the packet. The second lookup engines skip performing the second lookups for the packet in response to the first lookup engine finding the match of the first lookup key in the first database.

A search engine of a network device performs a lookup based on packet information associated with a packet being processed using a plurality of packet processing applications. The lookup includes one or more accesses to a lookup table that includes a plurality of interleaved entries associated with different ones of the packet processing applications. For each access, the search engine generates a search key to include at least a search string generated based on the packet information and an application identifier indicating a packet processing application for which the lookup is being performed, identifies an entry based on the search key, determines whether the search key matches search information in the identified entry, and when the search key matches the search information in the identified entry, identifies an action to be performed by the packet processor in connection with processing the packet by the packet processing application.

A physical layer (PHY) processor of a network device receives a timing message via an external network and generates a first timestamp using a first local-domain clock used by the PHY processor. The PHY processor transfers the timing message and the first timestamp to a packet processor of the network device via an internal communication link. The packet processor generates a second timestamp for the timing message using a domain-specific clock. The packet processor determines a delay value using the first timestamp, the delay value accounting for a time delay corresponding to the transfer of the timing message within the network device from the PHY processor to the packet processor. The packet processor adjusts the second timestamp using the delay value to generate an adjusted domain-specific timestamp for the timing message.

A source switching device in a switching system receives information measured by a target switching device in the switching system. The information is indicative of an amount of data received in a given amount of time by the target switching device via each of two or more first links coupled to the target switching device. The source switching device determines, based at least in part on the information received from the target device, a path, from among multiple paths from the source switching device to the target switching device, for transmission of a packet flow directed to the target switching device. The source switching device transmits, via the determined path for transmission of the packet flow to the target device, one or more packets belonging to the packet flow.

A packet processor of a network device repeatedly determines a fill level of a forwarding table that is populated with associations between network addresses and network interfaces of, or coupled to, the network device. The packet processor adjusts, based on the fill level of the forwarding table, a maximum rate according to which the packet processor is permitted to send messages to a central processing unit (CPU) coupled to the packet processor, the messages indicating network addresses that are to be stored in the forwarding table by the CPU. The packet processor of the network device receives packets via network links coupled to the network device; identifies new network addresses of the packets that are not in the forwarding table; and sends messages to the CPU at a rate that does not exceed the maximum rate, the messages indicating the new network addresses are to be added to the forwarding table.

An event message buffer queues event messages from a number of system components. Upon receiving an event message from a system component, the event message buffer compares the event message with a pending event message from the same component. If the event message is the same as the pending event message, the event message is not queued. If the event message differs from the pending event message, the event message is queued. Upon receiving a read request, the event message buffer only transmits the queued event message if it is different from the previously sent event message.