Microchip Technology Inc.

A method including attaching a plurality of hosts to separate partitions in a PCIe switch, at reset, routing all downstream ports of the PCIe switch internally to an internal partition of the PCIe switch, detecting, with an embedded CPU, all PCIe devices connected to the internal partition, and authenticating the devices with a control circuit. Upon authentication, connecting the PCIe devices to hosts connected to upstream ports of the PCIe switch via separate partitions.

A system includes a PCIe switch coupled to one or more hosts and coupled to at least one PCIe switch. A data packet may be received at the PCIe switch, the data packet to be moved from a source host to a destination host. Address information may be extracted from the data packet and may be compared with address information mapped to respective hosts in a routing table. The PCIe switch retrieves the destination buffer address from the destination host, communicate the destination address to the source host, program a bridge circuit to enable direct access of destination buffer to the source host allowing data to be bridged between the source host and the destination host.

A system may include a plurality of hosts coupled to respective PCIe ports, and the system may be coupled to a multi-function device (MFD). The apparatus may be coupled to one or more PCIe devices. The system may include a control circuit, the control circuit to enable an MFD sharing port to allow access to the MFD by the plurality of hosts. Individual hosts may have exclusive access to one or more portions of the MFD and the access of one host may be non-transparent to all other hosts.

System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

A computer-implemented method for synthesizing a digital circuit is disclosed. The method includes receiving a multi-threaded software program with at least one C++ thread; generating a register-transfer level (RTL) hardware description of the at least one C++ thread; and automatically inferring generation of parallel hardware RTL in response to receiving the at least one C++ thread.

A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.

System and method for analyzing CXL flits at read bypass detection logic to identify bypass memory read requests and transmitting the identified bypass memory read requests over a read request bypass path directly to a transaction/application layer of the CXL memory controller, wherein the read request bypass path does not include an arbitration/multiplexing layer and a link layer of the CXL memory controller, thereby reducing the latency inherent in a CXL memory controller.

System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.

A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.

System and method for sharing a PCIe endpoint device with a plurality of host computers, by allocating a quantum of time to a host computer of a plurality of host computers coupled to a PCIe switch, wherein the quantum of time identifies a duration of time during which the host computer has exclusive access to a shareable PCIe endpoint device coupled to the PCIe switch. Requests from the host computer are transmitted to an emulated PCIe endpoint device of the PCIe switch during the quantum of time and the requests are then redirected from the emulated PCIe endpoint device to the shareable PCIe endpoint device during the quantum of time allocated to the host computer.