Next Silicon Ltd

A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

An apparatus for executing a software program, comprising processing units and a hardware processor adapted for: in an intermediate representation of the software program, where the intermediate representation comprises blocks, each associated with an execution block of the software program and comprising intermediate instructions, identifying a calling block and a target block, where the calling block comprises a control-flow intermediate instruction to execute a target intermediate instruction of the target block; generating target instructions using the target block; generating calling instructions using the calling block and a computer control instruction for invoking the target instructions, when the calling instructions are executed by a calling processing unit and the target instructions are executed by a target processing unit; configuring the calling processing unit for executing the calling instructions; and configuring the target processing unit for executing the target instructions.

A method of processing incoming packets prior to complete reception, comprising receiving a pointer to one or more memory blocks allocated for storing one or more incoming packets to be written by one or more another controllers where each packet comprises one or more packet segments, determining all valid data values of fields contained in the packet segments. initializing one or more memory sections in the memory blocks which are mapped to the fields with predefined data pattern which are different from any of the valid values of the fields, checking continuously content of the memory sections, determining packet segment(s) were written in the memory block(s) responsive to detecting that the content of one or more of the memory sections do not match the one or more predefined data patterns, and processing one or more of the packets according to at least part of the received packet segment(s).

A method for caching memory comprising caching two data values, each of one of two ranges of application memory addresses, each associated with one of a set of threads, by: organizing a plurality of sequences of consecutive address sub-ranges in an interleaved sequence of address sub-ranges by alternately selecting, for each thread in an identified order of threads, a next sub-range in the respective sequence of sub-ranges associated therewith; generating a mapping of the interleaved sequence of sub-ranges to a range of physical memory addresses in order of the interleaved sequence of sub-ranges; and when a thread accesses an application memory address of the respective range of application addresses associated thereof: computing a target address according to the mapping using the application address; and storing the two data values in one cache-line of a plurality of cache-lines of a cache by accessing the physical memory area using the target address.

There is provided a memory, comprising: issuing an allocation operation for allocation of a region of a memory by a first process of a plurality of first processes executed in parallel on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process of a plurality of second processes executed in parallel on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein a same region of memory is allocated by the first process and released by the second process, wherein the first processes are concurrently attempting to issue the allocation operation and the second processes are concurrently attempting to issue the free operation.

An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration. The polynomial-based approximant and its adjusted set of coefficients for which the computed polynomial-based approximant complies with the constraint(s) may be output to one or more processing circuitries configured to approximate the function by computing the polynomial-based approximant.

A device for executing a software program by at least one computational device, comprising an interconnected computing grid, connected to the at least one computational device, comprising an interconnected memory grid comprising a plurality of memory units connected by a plurality of memory network nodes, each connected to at least one of the plurality of memory units; wherein configuring the interconnected memory comprises: identifying a bypassable memory unit; selecting a backup memory unit connected to a backup memory network node; configuring the respective memory network node connected to the bypassable memory unit to forward at least one memory access request, comprising an address in a first address range, to the backup memory network node; and configuring the backup memory network node to access the backup memory unit in response to the at least one memory access request, in addition to accessing the respective at least one memory unit connected thereto.

A joint scheduler adapted for dispatching prefetch and demand accesses of data relating to a plurality of instructions loaded in an execution pipeline of processing circuit(s). Each prefetch access comprises checking whether a respective data is cached in a cache entry and each demand access comprises accessing a respective data. The joint scheduler is adapted to, responsive to each hit prefetch access dispatched for a respective data relating to a respective instruction, associate the respective instruction with a valid indication and a pointer to a respective cache entry storing the respective data such that the demand access relating to the respective instruction uses the associated pointer to access the respective data in the cache, and responsive to each missed prefetch access dispatched for a respective data relating to a respective instruction, initiate a read cycle for loading the respective data from next level memory and cache it in the cache.

There is provided a computer implemented method of allocation of memory, comprising: issuing an allocation operation for allocation of a region of a pool of a memory by a first process executed on a first processor, sending a message to a second processor indicating the allocation of the region of the pool of the memory, wherein the first processor and the second processor access the region of the pool of the memory, issuing a free operation for release of the allocated region of the pool of the memory by a second process executed on a second processor, and releasing, by the first processor, the allocated region of the pool of the memory as indicated in the free operation, wherein the region of the pool of the memory allocated by the first process and released by the second process is a same region of memory.

An apparatus for computing functions using polynomial-based approximation, comprising one or more processing circuitries configured for computing a polynomial-based approximant approximating a function by executing one or more iterations. Each iteration comprising computing the polynomial-based approximant using scaled fixed-point unit(s) according to a constructed set of coefficients, minimizing an approximation error of the computed polynomial-based approximant compared to the function while complying with one or more constraints selected from a group comprising at least: an accuracy, a compute graph size, a computation complexity, and a hardware utilization of the processing circuitry(s), adjusting one or more of the coefficients in case the approximation error is incompliant with the constraint(s) and initiating another iteration. The polynomial-based approximant and its adjusted set of coefficients for which the computed polynomial-based approximant complies with the constraint(s) may be output to one or more processing circuitries configured to approximate the function by computing the polynomial-based approximant.