OMNIVISION TECHNOLOGIES, INC.

A pixel included in an image sensor includes a semiconductor substrate, a dielectric layer, a photodiode, a floating diffusion and a vertical transfer gate. The dielectric layer is disposed on the semiconductor substrate. The photodiode is formed in the semiconductor substrate. The floating diffusion is formed in the semiconductor substrate and separated from the photodiode. The vertical transfer gate is disposed coupling the photodiode to the floating diffusion and further disposed extending from the dielectric layer a depth into in the semiconductor substrate, wherein the vertical transfer gate includes a conductive material and a gate dielectric surrounding the conductive material, and the gate dielectric is disposed in the semiconductor substrate and levelled with a surface of the semiconductor substrate.

Bitline cut image sensors with ASIC clamping are disclosed. In some embodiments, an imaging system includes a pixel array and a replica voltage reference generation circuit. The pixel array can include a plurality of pixel circuits, select ones of the pixel circuits each including a row select transistor and a source follower transistor coupled between a supply voltage and the row select transistor. The replica voltage reference generation circuit can have an input coupled to the row select transistor. The replica voltage reference generation circuit can be configured to receive a voltage at the input and generate a clamp voltage that follows the voltage received at the input for each of one or more bitlines coupled to one or more outputs of the replica voltage reference generation circuit.

A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sampled and stored in a reset capacitor and a signal capacitor sequentially. In readout, the stored signal voltage is read out first to a comparing circuit to determine the best gain factor for the analog to digital converter (ADC) circuit to fully utilize the conversion range of the ADC to achieve a better signal to noise ratio. Once the better gain is determined and set for the ADC by comparing the signal voltage with a pre-determined threshold voltage, the same signal voltage is converted directly to become a digital signal value by the ADC. Then, the stored reset voltage is converted to a digital reset value by the ADC without changing the gain factor, to shorten the readout time.

A method of detecting a defocus of an image sensor and an image sensor applicable to perform the method are provided herein. The image sensor including a first subpixel and a second subpixel. The first subpixel includes m photodiode units and a first microlens structure overlaying the photodiode units, and m is an integer. The second subpixel includes m photodiode units and a second microlens structure overlaying the photodiode units. The first microlens structure is structurally different from the second microlens structure. First readout values of the photodiode units of the first subpixel are interpolated to positions of n of the photodiode units of the second subpixel to obtain interpolated values, wherein n is an integer. An imbalance value is obtained by using the interpolated values and second readout values provided by the n of the photodiode units of the second subpixel.

A method of correcting image data of an image sensor provided herein includes collecting a process window from the image sensor; obtaining weight factors of the process window in various directions based on readout values of the second photodiodes in the process window; obtaining interpolated values of the second photodiodes at positions of the first photodiodes in the first pixel groups in the process window by using the weight factors; and estimating a corrected value B target of a target first photodiode by an equation I: B target =G int ×(B mean /G mean ), wherein G int is the interpolated value of the second photodiodes at a position of the target first photodiode, B mean is a mean of readout values of first photodiodes in a corresponding first pixel group including the target first photodiode and G mean is a mean of the interpolated values of the second photodiodes at positions of the first photodiodes in the corresponding first pixel group.

An overflow integration capacitor is shared by a pair of photodiodes. Overflow gates are provided between respective photodiodes and the overflow integration capacitor. Further, in the overflow gates, potential barriers are set lower than respective ones of transfer gates in charge accumulation periods of the photodiodes.

A pixel cell includes a photodiode disposed in a semiconductor material. A floating diffusion is disposed in the semiconductor material. A transfer gate includes a vertical transfer gate structure disposed in the semiconductor material between the photodiode and the floating diffusion. The transfer gate is coupled between the photodiode and the floating diffusion. A passivation layer is disposed in the semiconductor material and proximate to the vertical transfer gate. The passivation layer has a region with a non-uniformly distributed doping profile proximate to the vertical gate structure such that a first doping concentration of the region in the passivation layer proximate to the vertical gate structure along a first direction is less than a second doping concentration of the region in the passivation layer proximate to the vertical gate structure along a second direction.

A sample and hold circuit includes a pixel level connection coupled to a pixel cell. In a voltage domain global shutter operation, a reset voltage and a signal voltage are sampled and stored in a reset capacitor and a signal capacitor sequentially. In readout, the stored signal voltage is read out first to a comparing circuit to determine the best gain factor for the analog to digital converter (ADC) circuit to fully utilize the conversion range of the ADC to achieve a better signal to noise ratio. Once the better gain is determined and set for the ADC by comparing the signal voltage with a pre-determined threshold voltage, the same signal voltage is converted directly to become a digital signal value by the ADC. Then, the stored reset voltage is converted to a digital reset value by the ADC without changing the gain factor, to shorten the readout time.

An image sensor including a plurality of photodiodes disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate, a first transfer gate and a second transfer gate that are each disposed proximate to the first side of the semiconductor substrate and coupled to a respective one of the plurality of photodiodes, and a floating diffusion region coupled to the first transfer gate and the second transfer gate is described. The first transfer gate is laterally separated from the second transfer gate by a separation distance. The floating diffusion region extends laterally within the semiconductor substrate a distance greater than the separation distance between the first transfer gate and the second transfer gate. The floating diffusion region includes a central portion surrounded by a peripheral portion. A first dopant concentration of the central portion is greater than a second dopant concentration of the peripheral portion.

Hybrid CIS/EVS image sensors are disclosed herein. In one embodiment, a pixel arrangement includes a plurality of pixels and a color filter array. Each of the plurality of pixels can include a photosensor, a floating diffusion, a transfer transistor, and an EVS transistor configured to selectively couple the photosensor to an event driven circuit corresponding to the pixel. The color filter array can include a plurality of color filters arranged in a mosaic pattern over photosensors of the plurality of pixels such that the photosensor of a first pixel of the plurality of pixels corresponds to a first color and the photosensor of a second pixel of the plurality of pixels corresponds to a second color different from the first color. The event driven circuits corresponding to the plurality of pixels can be (a) different from one another and (b) selectively coupled to one another via a common node.