UnfoldIPThemes

Company patents

Perceive Corporation

Perceive Corporation's patent strategy is heavily concentrated in Machine Learning & AI, comprising 96.2% of its portfolio, yet it surprisingly experienced a sharp 90.0% decline in patenting in this core area in 2025 after a 66.7% growth in 2024. This significant drop across nearly all categories, including Computer Hardware Architecture (-90.9% YoY in 2025) and Operating Systems & Program Control (-100.0% YoY in 2025), suggests a dramatic shift or slowdown in its patenting activity in 2025, rather than a strategic pivot to new emerging areas.

Patent Trend by Technology Area

Yearly patent publications since 2023

Product themes

Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.

53 US filings (since 2023) · 8 categories · 8 themes

AI/ML Hardware Acceleration

Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.

Machine Learning & AIComputer Hardware ArchitectureHardware Platform (Cooling, Power, Packaging)
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32since 2023
-90.5%YoY
Specialized Neural Network Architectures

Development and optimization of novel neural network layers or architectures specifically designed to improve performance or efficiency for computer vision tasks.

Computer Vision
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32since 2023
-95.0%YoY
Specialized Compute Architectures

Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.

Computer Hardware Architecture
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29since 2023
-94.7%YoY
Quantum Machine Learning

Developing and applying machine learning algorithms that leverage quantum computing principles, such as quantum circuits or autoencoders, for tasks like simulation or data processing.

Machine Learning & AI
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9since 2023
-60.0%YoY
Federated & Distributed ML

Methods for training machine learning models across multiple decentralized devices or servers while keeping data localized, often involving aggregation of model parameters and secure communication.

Machine Learning & AI
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4since 2023
n/a
Compiler Optimization & Code Analysisfiltered

Techniques employed within compilers or related tools to analyze program code, identify entities for compilation, and optimize execution on target hardware, including reconfigurable systems, to improve performance or resource efficiency.

Software Development & Compilers
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4since 2023
n/a
Large Model Text Generation

Techniques for generating human-like text or other content using large pre-trained models, often involving prompt engineering, speculative decoding, or multi-modal inputs for content creation.

Machine Learning & AI
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1since 2023
n/a
Efficient Visual Feature Extraction

Algorithms and hardware optimizations for rapidly identifying and characterizing relevant visual features (e.g., objects, motion, gradients) from images or video streams, often integrating machine learning for feature representation and recognition, with a focus on real-time performance and reduced computational cost.

Pattern Recognition & ML Models
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1since 2023
n/a

Patents

Showing 1-4 of 4

Compiler Optimization & Code Analysis
Page 1 of 1
US 11941533 B1GRANTED
G06N3/04

Compiler for performing zero-channel removal

Filed:2019-07-29Pub:2024-03-26
Applicant:Perceive Corporation

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. The compiler, as part of generating the graph, in some embodiments, determines whether any set of channels contains no non-zero values (i.e., contains only zero values). For sets of channels that include no non-zero values, some embodiments perform a zero channel removal operation to remove all-zero channels wherever possible. In some embodiments, zero channel removal operations include removing input channels, removing output channels, forward propagation, and backward propagation of channels and constants.

US 11868901 B1GRANTED
G06N3/10

Compiler for optimizing memory allocations within cores

Filed:2019-07-29Pub:2024-01-09
Applicant:Perceive Corporation

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the graph includes nodes representing options for implementing each layer of the machine-trained network and edges between nodes for different layers representing different implementations that are compatible. The graph is used, in some embodiments, to select an optimum set of cores for implementing the received machine-trained network. The compiler, in some embodiments, optimizes memory storage such that input and output layers of a single layer are not stored in a same memory unit. Such an optimization, in some embodiments, avoids attempting to read and write from a same memory unit within a core in a single clock cycle.

US 11625585 B1GRANTED
G06N3/08

Compiler for optimizing filter sparsity for neural network implementation configuration

Filed:2019-07-29Pub:2023-04-11
Applicant:Perceive Corporation

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). In some embodiments, the compiler determines whether sparsity requirements of channels implemented on individual cores are met on each core. If the sparsity requirement is not met, the compiler, in some embodiments, determines whether the channels of the filter can be rearranged to meet the sparsity requirements on each core and, based on the determination, either rearranges the filter channels or implements a solution to non-sparsity.

US 11615322 B1GRANTED
G06N3/10

Compiler for implementing memory shutdown for neural network implementation configuration

Filed:2019-07-29Pub:2023-03-28
Applicant:Perceive Corporation

Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the graph includes nodes representing options for implementing each layer of the machine-trained network and edges between nodes for different layers representing different implementations that are compatible. The compiler of some embodiments is also responsible for generating instructions relating to shutting down (and waking up) memory units of cores. In some embodiments, the memory units to shutdown are determined by the compiler based on the data that is stored or will be stored in the particular memory units.

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