Company patents
PHISON ELECTRONICS CORP.
PHISON ELECTRONICS CORP. surprisingly shows a strong and sustained focus on Input/Output & User Interfaces, representing 59.0% of its portfolio, despite a recent decline of 11.1% in 2025. While Memory & Storage (Static) remains a significant area at 23.7%, the dramatic 200.0% growth in Computer Hardware Architecture patents in 2025 suggests an emerging strategic shift towards core computing infrastructure, even with partial data showing a decline so far in 2026.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
173 US filings (since 2023) · 9 categories · 11 themes
Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.
Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.
Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.
Techniques and circuits for accurately identifying various electrical faults, such as ground faults, overcurrent, short circuits, switch malfunctions, or electrostatic discharge (ESD) events, often utilizing sensors, signal processing, and diagnostic algorithms.
Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.
Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.
Methods for designing, transmitting, and utilizing specific reference signals (e.g., DMRS, SRS, PT-RS) to enable accurate channel estimation, interference measurement, synchronization, or sensing in wireless communication systems.
Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.
Techniques for encoding digital data onto analog carrier signals using complex constellation diagrams, multi-level signaling, or layered approaches, often combined with error correction codes, to achieve higher data rates, improved spectral efficiency, or extended range.
Specialized circuits and devices designed to protect electrical and electronic systems from transient overvoltages caused by electrostatic discharge (ESD) or power surges, often involving suppressor diodes, gas discharge tubes (GDTs), or voltage clamping mechanisms.
Intelligent control systems that manage the connection and disconnection of power, including pre-charging capacitive loads, reclosing after faults, or isolating parts of a grid based on detected conditions, often involving smart switches and relays with adaptive logic.
Patents
Showing 171-180 of 235
Memory System Performance & Reliability