PHISON ELECTRONICS CORP.

An encoding control method, a memory storage device, and a memory control circuit unit are provided. The encoding control method includes: obtaining write data; performing an encoding operation by an encoding circuit to generate first parity data and second parity data according to the write data, in which the second parity data is not generated according to the first parity data; sending a first write command sequence to instruct a storage of the write data, the first parity data, and the second parity data in a rewritable non-volatile memory module, in which the first parity data is used to perform a decoding operation with the write data, and the second parity data, along with the first parity data, is used to perform the decoding operation with the write data.

A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: recording a random read count for each of multiple first physical units, in which each first physical unit stores valid data; initiating a data merging process; selecting multiple source physical units from the first physical units according to the random read count; and moving valid data in the source physical units to a target physical unit.

A memory management method, including: acquiring multiple architecture parameters of an artificial intelligence model; obtaining a memory allocation size used in a training process of the artificial intelligence model according to the multiple architecture parameters; configuring a target memory region in random access memory according to the memory allocation size, wherein train processing stage in the training process of the artificial intelligence model shares the target memory region; and temporarily storing intermediate data corresponding to each train processing stage of the training process of the artificial intelligence model in the target memory region, wherein the intermediate data is transferred between accelerator processor module, the random access memory, and a storage device. Thereby, the present invention can automatically calculate the optimized memory allocation size, and through the design of shared memory space, effectively improve memory fragmentation issues.

A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.

An error handling method, a memory storage device, and a memory control circuit unit are provided. The error handling method includes: calculating a first decoding rate of a first error handling process, where the first error handling process includes a plurality of decoding operations performed based on a first order; and in response to the first decoding rate being less than a first threshold, switching the first error handling process to a second error handling process, where the second error handling process includes a plurality of decoding operations performed based on a second order, where a decoding capability of a first decoding operation indicated by the second order is better than a decoding capability of a first decoding operation indicated by the first order.

A memory management method is provided for a rewritable non-volatile memory module. The method includes: initiating a data merging operation; selecting a source physical unit and a target physical unit from the rewritable non-volatile memory module to perform the data merging operation; determining whether to create a backup table corresponding to a logical-to-physical mapping table; if it is determined to create the backup table, copying first data located at a first physical address in the source physical unit to a second physical address in the target physical unit, and recording the second physical address in the backup table; and determining whether to update the second physical address to the logical-to-physical mapping table based on information in the backup table.

A training method for a machine learning model and a host system are provided. The host system includes a rewritable non-volatile memory module. The training method includes: executing a training process of the machine learning model, which includes, in an iteration at an epoch of the training process, storing transient data and backtracking data generated by the iteration in the rewritable non-volatile memory module; and in response to an abnormality occurring in the host system which causes an interruption in the iteration, reading the transient data and the backtracking data from the rewritable non-volatile memory module, determining a stage of the iteration based on the backtracking data, and resuming the stage according to the transient data.

A data check method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. A connection between a memory storage device and a host system is established. First check data is generated according to first data. The first check data is maintained in the memory storage device. A cross-device write command is sent through the connection to store the first data into a memory in the host system. After the cross-device write command is sent, a cross-device read command is sent through the connection to read back the first data from the memory in the host system. In response to cross-device reading meeting a check trigger condition, a first check operation is performed on the read-back first data according to the check data to check whether the read back first data is abnormal. In response to the cross-device reading not meeting the check trigger condition, the first check operation is skipped.

A memory control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a state of the memory storage device; and adjusting an operation mode of the memory storage device according to the state of the memory storage device, wherein the operation mode includes a first operation mode and a second operation mode, and a first waiting time before the memory storage device entering a power saving mode in the first operation mode is longer than a second waiting time before the memory storage device entering the power saving mode in the second operation mode.