Powerchip Semiconductor Manufacturing Corporation

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

The present invention provides a silicon capacitor structure, including a substrate, an interlayer dielectric (ILD) layer on the substrate, a capacitor recess extending from a surface of the ILD layer into the substrate, a capacitor in the capacitor recess, wherein the capacitor includes a bottom electrode on a surface of the capacitor recess, a capacitive dielectric layer on a surface of the bottom electrode, and a top electrode on a surface of the capacitive dielectric layer and filling up the capacitor recess.

The disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a substrate including a cell region and a pick-up region adjacent to the cell region, word lines embedded in the substrate, arranged in a first direction, extending in a second direction crossing the cell region and the pick-up region, and each including a first segment in the cell region and a second segment in the pick-up region, an insulation layer embedded in the substrate on each word line and, and a conductive contact on the second segment of each word line. The first segment includes a first top surface contacting the insulation layer. The second segment includes a second top surface contacting the conductive contact and a third top surface contacting the insulation layer. The second top surface has a level height different from a level height of the first top surface.

A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.

Disclosed are a testing method and a testing system. The testing method is configured to scan a three-dimensional memory chip. The three-dimensional memory chip includes a plurality of memory chips stacked with each other. The testing method includes: dividing each memory chip into a plurality of memory blocks; testing each memory block to detect a total failed first signal line quantity from a plurality of first signal lines extending along a first direction in each memory block, and to detect a total failed memory cell quantity of each memory block; and determining a failed bit quantity threshold according to the total failed first signal line quantity, and comparing the total failed memory cell quantity with the failed bit quantity threshold, to accordingly determine whether to set a marked first signal line quantity.

A semiconductor structure includes a plurality of first wafers and a through-substrate via (TSV). The plurality of first wafers include a plurality of conductive connection lines. Each of the conductive connection lines is located in the corresponding first wafer. The through-substrate via passes through the plurality of first wafers and a plurality of end portions of the plurality of conductive connection lines. The plurality of end portions are embedded in the through-substrate via.

Disclosed are a testing method and a testing system. The testing method is configured to scan a three-dimensional memory chip. The three-dimensional memory chip includes a plurality of memory chips stacked with each other. The testing method includes: dividing each memory chip into a plurality of memory blocks; testing each memory block to detect a total failed first signal line quantity from a plurality of first signal lines extending along a first direction in each memory block, and to detect a total failed memory cell quantity of each memory block; and determining a failed bit quantity threshold according to the total failed first signal line quantity, and comparing the total failed memory cell quantity with the failed bit quantity threshold, to accordingly determine whether to set a marked first signal line quantity.

A stack memory device and its operation method are provided. The stack memory device includes a memory chip having memory units, a logic chip bonded to the memory chip and an external port module. The logic chip has an OTP circuit storing operation information of the memory units; a memory controller, a peripheral controller, shifters, and selectors. Each o shifter receives a command, data and address from the peripheral controller, and transfers the command, data and address to each memory unit with a shift amount with respect to a clock signal. The peripheral controller is in a standby status when the stacked memory device is in an operation status, or the peripheral controller performs a memory test or controls of the non-volatile memory circuit.

A stacked memory with a timing adjustment function is provided, including a logic chip; a memory chip coupled to the logic chip in a face-to-face manner and including plural memory tiles; plural timing adjustment devices, respectively provided in each memory tile, wherein for each memory tile, each timing adjustment device further includes a first timing adjustment device that is configured to adjust setup times and hold times for a command and an address with respect to an edge of a clock signal and a second timing adjustment device that is configured to adjust a setup time and a hold time for input data with respect to the edge of the clock signal.

Disclosed is a semiconductor structure including a substrate, a first conductive layer, a second conductive layer, a work function layer, a filling layer, and a first dielectric layer. The first conductive layer is located in the substrate. The second conductive layer is located between the first conductive layer and the substrate. The work function layer is located on the first conductive layer. A cross-sectional shape of the work function layer is U-shaped and has a recess. The filling layer is located in the recess. A top surface of the filling layer is higher than a top surface of the work function layer. The first dielectric layer is located between the second conductive layer and the substrate and between the work function layer and the substrate.