Company patents
pSemi Corporation
pSemi Corporation's patent strategy shows a broad focus on semiconductor technologies, with Amplifiers, Pulse / Digital Logic Circuits, and Power Conversion (DC/AC, DC/DC) collectively accounting for over 80% of its portfolio. While there was a notable 100.0% YoY growth in Semiconductor Packaging & Encapsulation in 2024 and a 133.3% YoY growth in Transistor & Device Structure in 2024, the company appears to be shifting priorities, with significant declines across most categories in 2025 and so far in 2026, including a -100.0% YoY decline in Integrated Circuit Layout & Arrangement and Transistor & Device Structure in 2026.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
591 US filings (since 2023) · 12 categories · 39 themes
Focuses on novel circuit configurations for DC-DC, DC-AC, or AC-DC conversion, often involving resonant operation, multi-level structures, or switched capacitors to improve efficiency, power density, or voltage conversion ratios.
Amplifier designs that allow for dynamic adjustment of their operating characteristics, such as gain, impedance, or amplification path, based on control signals, input conditions, or desired performance modes.
Circuit designs and control techniques focused on maximizing the power conversion efficiency of amplifiers, especially for radio frequency (RF) or audio applications, often involving load modulation, envelope tracking, or specific amplifier classes (e.g., Class-D, Doherty).
Digital logic and control circuits for managing power delivery, driving various loads (e.g., inductive, display elements), converting power, and protecting against over-voltage or electrostatic discharge. Includes gate drivers for power FETs and voltage level shifters.
Circuitry and techniques specifically designed to amplify weak signals while minimizing the introduction of additional noise and maintaining high linearity, often incorporating impedance matching, parasitic neutralization, or protection circuits.
Methods and circuits to detect and compensate for various imperfections in amplifier operation, such as DC offset, gain errors, phase errors, duty-cycle errors, or input error components, to improve accuracy and signal integrity.
Techniques and circuits designed to regulate output, manage input variations, mitigate resonance, or ensure stable operation of power converters under diverse load and source conditions. This includes adaptive, predictive, or fault-tolerant control schemes.
Antennas engineered to operate effectively across a wide continuous range of frequencies (broadband) or multiple distinct frequency bands, often requiring specific radiating element geometries or impedance matching circuits.
Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.
Specialized amplifier types designed for converting current to voltage (transimpedance) or voltage to current (transconductance), often featuring virtual ground configurations, precise gain setting, and compensation for input/output characteristics.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.
Integration of power converters with energy storage devices (batteries, supercapacitors) or grid interfaces, often involving AC/DC conversion, power flow management, and fault handling for hybrid power systems or specific applications like EVs or PV.
Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.
Circuits and techniques for generating, synchronizing, interpolating, and recovering high-frequency clock signals and high-speed data streams, often involving reduced propagation delay, multi-level signaling, and robust sampling mechanisms.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Techniques and structures used to reduce unwanted electromagnetic coupling, scattering, or interference between multiple antennas, different frequency bands, or sensitive electronic components within a device.
Systems and methods for electronically steering or shaping antenna beams by controlling the phase and amplitude of signals fed to individual elements in an array, including calibration techniques and multi-antenna configurations.
Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.
Circuits designed to transform the impedance of a source to match the impedance of a load, maximizing power transfer or minimizing signal reflections, often involving inductors, capacitors, and transformers.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Methods and structures for encapsulating, interconnecting, and integrating impedance network components, particularly acoustic filters, into larger modules or systems.
Specialized digital and mixed-signal circuits for controlling and reading out quantum bits (qubits), including generating precise modulated RF signals and integrating with photonic components for quantum operations.
Design and manufacturing techniques for incorporating antenna structures directly into electronic devices, product housings, or materials, often under constraints of space, aesthetics, or environmental factors.
Techniques and circuits designed to identify, compensate for, or correct non-linearities, offsets, and other imperfections in signal processing paths, particularly within analog-to-digital, digital-to-analog, or digital-to-time converters.
Devices utilizing piezoelectric materials to generate and filter acoustic waves, often for radio frequency applications, including surface acoustic wave (SAW) and bulk acoustic wave (BAW) structures.
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Devices and methods for accurately measuring or monitoring electrical current draw and power usage in various systems, often for control, optimization, or safety purposes.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Techniques for designing and manufacturing compact, multi-functional magnetic components, such as inductors, transformers, and coils, often involving embedded structures, multilayer designs, or shared magnetic circuits to achieve higher power density or smaller form factors.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Techniques and systems for precisely measuring electrical or electromagnetic properties of materials or components, often involving specialized resonators, waveguides, or multi-range measurement systems to ensure accuracy.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Digital logic circuits designed to interface with analog sensors or signals, including comparators, input buffers, differential input stages, and logic for processing sensor outputs (e.g., capacitance, optical, touch) for detection or measurement.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Patents
Showing 1-10 of 17
Gate Stack & Dielectric Engineering