Rambus Inc.

As information is written to a memory device stack, partial parity information is calculated by the non-parity devices in the stack from the information being written to that device and parity information received from the next lower device in the stack (if any). The partial parity information calculated by each non-parity device is transmitted to the next higher device in the stack so that it may perform a partial parity calculation using the partial parity information collectively calculated by the devices lower in the stack. Once complete parity has been collectively calculated by all of the non-parity devices in the stack, the complete parity information is stored by the parity memory device. The complete parity information may be used to recover or reconstruct data from a failing device in the stack by calculating and transmitting parity information from non-failing devices to the failing device and/or the parity device.

A memory buffer services commands from a host to access data in a memory using parity bits augmented with metadata for improved error correction and detection (EDC). The memory buffer performs EDC-protocol translation so EDC can be optimized for host-side and memory-side correction and detection. The memory buffer also services each host-side memory transaction with two or more memory-side transactions to efficiently read, write, and store metadata for each requested cache-line access.

Refresh management commands are issued to a memory device in order to cause the refresh of rows in the vicinity of one or more rows being “hammered.” These refresh management commands are each associated with respective row addresses that indicates the row(s) to be refreshed in order to mitigate the likelihood of data being corrupted by “row hammer.” In an embodiment, the refresh management commands are issued in response to a varying number of activate (ACT) commands having been issued since the last refresh management command. The row selected for a given refresh management command may be selected based on rows that have recently been activated. The selection may be based on “pools” of recently activated rows where these pools are of unequal size. The selection from a given pool may be based on algorithmic and/or random techniques.

Row addresses received by a module are mapped before being received by the memory devices of the module such that row hammer affects different neighboring row addresses in each memory device. Thus, because the mapped respective, externally received, row addresses applied to each device ensure that each set of neighboring rows for a given row address received by the module is different for each memory device on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each memory device. This has the effect of confining the row hammer errors for each row that is hammered to a single memory device per externally addressed neighboring row. By confining the row hammer errors to a single memory device, the row hammer errors are correctible using a SDDC scheme.

An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.

Aspects and implementations include systems and techniques that implement efficient indexing and access to sparse neural network parameters. In one example, a memory system includes a buffer chip communicatively coupled to the one or more memory units. The buffer chip is to obtain a first index associated with positions of a plurality of elements of a sparse matrix (SM) along a first dimension of the SM and obtain a second index associated with positions of the plurality of the elements of the SM along a second dimension of the SM. The buffer chip is further to obtain, using the first index and the second index, memory addresses of the plurality of the elements of the SM stored in the one or more memory units, and retrieve, based on the memory addresses, the plurality of the elements of the SM from the one or more memory units.

A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range, and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.

An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies. The base die is interconnected vertically with the DRAM dies using through-silicon via (TSV) connections that carry data and control signals throughout the stack. The data signals of the DRAM dies are interconnected vertically to the base die using separate, non-overlapping, sets of TSVs. In a first configuration, each die in the stack is accessed using unique chip identification numbers. In a second configuration, a single chip identification number is used to access two or more dies in the stack. At least one bit of the chip identification number may be used in determining the row being accessed. Data communicated with dies in the stack may be communicated with the base die using non-overlapping sets of data signal connections.

The internal row addressing of each DRAM on a module is mapped such that row hammer affects different neighboring row addresses in each DRAM. Because the external row address to internal row address mapping scheme ensures that each set of neighboring rows for a given externally addressed row is different for each DRAM on the module, row hammering of a given externally addressed row spreads the row hammering errors across different externally addressed rows on each DRAM. This has the effect of confining the row hammer errors for each row that is hammered to a single DRAM per externally addressed neighboring row. By confining the row hammer errors to a single DRAM, the row hammer errors are correctible using a single device data correct (SDDC) scheme.