Rambus Inc.

A memory controller includes a processing device to execute latency tracking logic to determine respective latencies for a plurality of memory access requests in a memory access queue. The latency tracking logic further determines respective bandwidth usages of the memory controller corresponding to the plurality of memory access requests and stores respective counts of the plurality of memory access requests having respective latencies corresponding to a plurality of latency ranges for the respective bandwidth usages. The latency tracking logic further configures operations of the memory controller in view of the respective counts for the respective bandwidth usages.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range, and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.

Multiple multi-channel dynamic random access memory (DRAM) die are stacked with each other. Each DRAM die of the stack includes two sets of I/O pads for each channel on the die. Based on the rotational orientation of a respective die in the stack, one of the two sets of I/O pads are used for data communication, and the other set is not used. The set of I/O pads that will be closest to the memory controller may be selected thereby shortening the signal traces between the controller and the die. The die in the stack may have one of two rotational orientations. A first one of the two sets of I/O pads are used by the die having a first rotational orientation (e.g., 0°), and a second one of the two sets of I/O pads are used by the die having a second rotational orientation (e.g., 180°).

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory controller is disclosed. The memory controller includes write queue logic that has first storage to temporarily store signal components of a write operation. The signal components include an address and write data. A transfer interface issues the signal components of the write operation to a bank of a storage class memory (SCM) device and generates a time value. The time value represents a minimum time interval after which a subsequent write operation can be issued to the bank. The write queue logic includes an issue queue to store the address and the time value for a duration corresponding to the time value.

A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a read command to retrieve read data from a memory. Memory interface circuitry couples to the memory. Data freshness authentication circuitry performs a freshness verification operation on the read data. Read data forwarding circuitry, in a skid mode of operation, transmits the read data to the host prior to completion of the freshness verification operation.

Row hammer is mitigated by issuing, to a memory device, mitigation operation (MOP) commands in order to cause the refresh of rows at a specified vicinity of a suspected aggressor row. These mitigation operation commands are each associated with respective row addresses that indicate the suspected aggressor row and an indicator of which neighbor row in the vicinity of the suspected aggressor row is to be refreshed. The mitigation operation commands are issued in response to a fixed number of activate commands. The suspected aggressor row is selected by randomly choosing, with equal probability, one of the N previous activate commands to supply its associated row address as the suspected aggressor row address. The neighbor row may be selected randomly with a probability that diminishes inversely with the distance between the suspected aggressor row and the neighbor row.

A system and method for performing a low overhead refresh management of a memory device. The method includes receiving, by a controller from a dynamic random access memory (DRAM) device via a feedback interface, a signal indicative of an occurrence of a row hammer event. The method includes determining, by the controller based on the signal, whether to schedule a refresh event. The method includes sending, by the controller responsive to determining whether to schedule the refresh event, a first command to the DRAM device to execute a refresh operation.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a memory controller via a bus. The module includes at least two non-volatile memory devices, and a buffer disposed between the pin interface and the at least two non-volatile memory devices. The buffer receives non-volatile memory access commands from the memory controller that are interleaved with DRAM memory module access commands.