REBELLIONS INC.

An inference task method of a Large Language Model (LLM) inference task system, the method comprising: tokenizing an input query of a user, deriving a predicted query based on the tokenized input query, wherein the predicted query is a sentence predicted based on the input query, determining whether an inference task is performed for the predicted query, and when it is determined that the inference task is performed for the predicted query, performing the inference task for the predicted query to generate an answer to the predicted query.

Provided is an electronic device, including a first chiplet including a system bus, a first interconnect module, and a second interconnect module, and a second chiplet connected to the first chiplet through at least one of a first interconnect interface connected to the first interconnect module or second interconnect interface connected to the second interconnect module, in which, in response to determining that a communication failure occurs between the first chiplet and the second chiplet, at least a part of a transfer path through which information is transmitted from the first chiplet to the second chiplet is changed.

Provided is a chiplet including an interconnect module for connecting to another chiplet, a bus interface for connecting to at least one functional module in the chiplet, and an address remapper block connected to the interconnect module and the bus interface, in which the address remapper block receives a transaction and remaps a destination address in the transaction.

Provided is a method for shifting data within a memory, which is performed by a direct memory access (DMA) controller, and which includes receiving a task associated with an operation of shifting target data stored in a first area of a memory connected to the DMA controller to a second area of the memory, based on the task, generating sub-tasks associated with operations of shifting data chunks divided from the target data to the second area, determining data chunk groups each including at least one data chunk by grouping the data chunks, determining a priority of each of the data chunk groups based on an address of the first area and an address of the second area, and shifting the data chunk groups to the second area in sequence according to the determined priority.

A method for high frequency trading is provided, which is performed by one or more processors, and includes generating input data based on market data for a target item, generating prediction data for the target item for each of a plurality of future time points by inputting the generated input data to a machine learning model, and generating order data for the target item based on the generated prediction data.

According to one or more embodiments of the present disclosure, a neural cluster includes a plurality of neural core units each including a neural core configured to process a neural network operation, a plurality of shared memory units each including a shared memory shared by the plurality of neural core units, and a mesh network for connecting the plurality of neural core units and the plurality of shared memory units, wherein the plurality of shared memory units are arranged in a central portion of the neural cluster, and the plurality of neural core units are arranged symmetrically above and below a shared memory area where the plurality of shared memory units are arranged.

A neural processing device is provided. The neural processing device comprises: a processing unit configured to receive an input activation and a weight and perform a two-dimensional matrix calculation with the input activation and the weight to generate an output activation, a first memory, and a load-store unit (LSU) configured to perform memory access operations between the first memory and a second memory. The memory access operations include a main memory access operation for a current processing operation that is performed by the processing unit, and a standby memory access operation for a standby processing operation that is performed by the processing unit after the current processing operation. A level of the first memory is equal to a level of the processing unit, and a level of the second memory is different from the level of the first memory.

A neural processor and a method for fetching instructions thereof are provided. The neural processor includes a local memory in which weights, input activations, and partial sums are stored, a processing unit configured to compute the weights, the input activations, and the partial sums, and a local memory load unit configured to load the weights, the input activations, and the partial sums from the local memory into the processing unit, wherein the local memory load unit includes an instruction fetch unit configured to fetch instructions included in a program of the local memory load unit for loading any one of the weights, the input activations, or the partial sums from the local memory, and an instruction execution unit configured to generate control signals for executing instructions fetched by the instruction fetch unit.

An accelerator system according to an embodiment of the present disclosure includes at least one SOC and a board level management module configured separately from the at least one SOC and connected to the at least one SOC, and the board level management module is configured to monitor average power consumption of the at least one SOC according to a predetermined period during a duration of a task in response to the task being performed in the at least one SOC, determine whether monitored average power consumption is within a threshold range determined based on a power consumption budget defined for the duration, and transmit, to the at least one SOC, a first control signal related to reduction of power consumption of the at least one SOC in response to determining that the average power consumption is within the threshold range.

A chiplet system including a plurality of chiplets is disclosed. The chiplet system includes a first chiplet comprising a first interface for communicating with a first external device and a first RoT (root of trust) in which tamper-resistant first data is stored, and a second chiplet comprising a second interface for communicating with a first memory, a second RoT in which tamper-resistant second data is stored, and a first computation module that performs computation using data stored in the first memory.