SambaNova Systems, Inc.

A DMA engine may process a work queue (WQ) configured to store work queue elements (WQEs). A processor may write a work queue element (WQE) to the WQ, the WQE including a jump_wait indicator. The DMA engine may be configured to enter a jump_pause state in response to processing the WQE and determing that the jump_wait indicator is set. The DMA engine may be configured to identify a one of the WQEs based at least in part on a jump offset in a trigger message. The DMA engine may be configured to enter a run state and to begin processing the one of the WQEs in response to receiving the trigger message. The DMA engine may be configured to transfer a block of data between a memory and a network interface in response to processing the one of the WQEs.

A system for allocating reconfigurable processor resources to virtual functions includes a runtime processor coupled to a multi-die reconfigurable processor via a communication link. The reconfigurable processor comprises first and second dies arranged in a package, each die having arrays of coarse-grained reconfigurable units. The runtime processor receives resource allocation requests for virtual functions, determines resource requirements for each virtual function including number of arrays and memory capacity, evaluates available resources across the first and second dies, and allocates arrays from the first die, the second die, or both dies to each virtual function based on the resource requirements and available resources. The runtime processor configures communication link interfaces to provide the allocated arrays to virtual function drivers, enabling efficient multi-tenant operation of the reconfigurable processor with optimized resource utilization and isolation between virtual functions.

A method for integrating buffer views into buffer access operations in reconfigurable computing environments. The method includes detecting, in a buffer allocation statement comprising a tensor indexing expression, a buffer view indicator and one or more buffer view parameters. The buffer view parameters are lowered into the tensor indexing expression, according to the buffer view indicator, to produce a modified tensor indexing expression. The buffer view indicator is removed from a buffer allocation statement to produce a modified buffer allocation statement.

This application provides an example system and an example method for initiating direct memory access from a dataflow graph running across multiple coarse-grained reconfigurable processors (CGRPs) using message based triggers. One example CGRP comprises a set of CGR units (CGRUs) including a first CGRU, a top-level network (TLN), an external network interface (ENI) and an external network shim (Eshim) including an external direct memory access (EDMA) engine. The Eshim to receive a first message over the TLN. The Eshim also to read a current work queue entry (WQE) of a first work queue (WQ) of a set of WQs based on a physical WQ identification (ID) and a WQ start operation of the first message. The Eshim further to initiate a data transfer utilizing both the TLN and ENI based on information in the current WQE.

This application provides an example system and an example method for chaining DMA transfers from a dataflow graph running across multiple CGRPs. One example first CGRP comprises a first set of coarse-grained reconfigurable units (CGRUs) including a first CGRU, a first external network, a second external network, a first external memory interface (EMI), and first external network shim (Eshim). The first Eshim to receive over the first external network a first transfer (TX) frame of a DMA transfer comprising first frame data from a second CGRP, initiate a memory write of the first frame data to a first memory. The first Eshim to receive a first completion message that indicates the memory write has completed, and to trigger a second DMA transfer of a second TX frame comprising a first subset of the first frame data to a third CGRP utilizing the second external network.

A computer system includes an array of reconfigurable processor blocks which execute fragments of a larger data processing operation. An array controller distributes a control signal to the reconfigurable processors in the array and receives control signals for the respective execution fragments. The control signal may include quiesce logic or other control methods to execute the effective execution fragments of the larger data processing operation when individual processors become available.

A reconfigurable processor is disclosed, featuring an array of configurable units interconnected by a bus system. Each configurable unit includes a configuration data store structured as a shift register that includes individually addressable argument registers. Program load logic is responsible for receiving sub-files of configuration data through the bus system and sequentially shifting them into the configuration data store, including the argument registers. Argument load logic is designed to receive argument data via the bus system and directly load it into the argument registers without the need for shifting through the shift register.

A system and method for memory unit partitioning for reconfigurable dataflow computing systems includes a parser that receives and parses source code for a reconfigurable dataflow processor, a tensor expression extractor that extracts tensor indexing expressions from the source code, a logical memory constraint generator that converts the tensor indexing expressions to logical memory indexing constraints, a grouping module that groups the logical memory indexing constraints into concurrent access groups, and a memory partitioning module that determines a memory unit partitioning solution for each concurrent access group.

In some aspects, a program is executed on a coarse-grained reconfigurable (CGR) processor. The CGR determines that the program produces an output that includes a variable length tensor, determines a maximum size of the variable length tensor and sets, based on the maximum size, a maximum of a counter associated with the program. The counter is set to an initial value of zero. The CGR initiates execution of the program, causing the program to receive an input tensor. Based on determining that the program is operating on a first portion of the input tensor, the CGR performs an update to the counter, to create an updated counter, and communicates the updated counter to one or more consumers within the program. After determining that the program has completed operating on the input tensor, a final size of the output is communicated to one or more downstream consumers external to the program.

A system comprises an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), and a compiler configured to receive a tensor including a plurality of memory access patterns of a first type (read) and a second type (write) located in a logical memory of the compiler. Each memory access pattern includes a memory access particular to that type. The compiler is configured to create a plurality of duplicates of the tensor and assign one or more contexts of any type to the duplicate tensors, such that no two contexts of the same type are in the same duplicate tensor.