Sandisk Technologies, Inc.

A semiconductor device includes a number of stacked semiconductor dies and a partial, controlled amount of underfill material between each semiconductor die. The underfill material fills a central portion of the space between adjacent semiconductor dies, leaving an edge gap in the space around the underfill material. After the die stack has been completed, the stack may be encapsulated in mold compound. In addition to covering the surfaces of the die stack, the mold compound fills the edge gap so that all spaces between dies are filled.

A data storage device includes a memory die failure anticipation system that proactively determines when a plane of a memory die and/or the memory die itself, is likely to fail. To proactively determine whether the memory die is likely to fail, the memory die failure anticipation system periodically monitors performance characteristics of one or more voltage pumps of the memory die. If the memory die failure anticipation system determines, based on the performance characteristic(s), that the memory die is failing, the memory die failure anticipation system initiates a relocation operation that transfers data that is stored on the failing memory die to another memory die.

To determine NAND memory blocks with an upper tail or a lower tail of select gate threshold voltage levels, a tail detection read is introduced into the erase process. To minimize the time penalty on the erase process, the tail detection read is only performed for a specified loop in the erase verify process. More specifically, in an erase process using an algorithm of a loop of applying an erase pulse followed by an erase verify operation, an erase loop count is maintained and incremented at each loop. If the block fails erase verify, before looping back for the next erase pulse a tail detection read is performed, but only if the erase loop count equals a specified value (which can be a settable parameter); otherwise, the tail detection read is not performed.

Rather than allocating bandwidth to various host devices or functions in a multi-device system based upon the amount of data transferred, the bandwidth is allocated based upon the power consumed to execute a command. While two different commands may transfer an equal amount of data, the two different commands may consume different amounts of power. For example, one command may involve utilizing encryption while the other command may not use encryption. Utilizing encryption involves using more power than when encryption is not utilized. By considering power consumption on a per command basis, bandwidth allocation can be fair to ensure quality of service (QoS) is high.

A thickness of a signal trace on a printed circuit board (PCB) or a substrate is increased by intentionally forming a solder bridge on a surface of the signal trace during a reflow process in which a flip chip die or other computing component is mounted to the PCB or the substrate. Specifically, adjacent interconnects of the flip chip die are coupled to the same signal trace on the PCB or the substrate. During the reflow process, solder associated with each interconnect flows into a space or area defined by the adjacent interconnects and forms a solder bridge within the space, thereby increasing a thickness of the signal trace.

In wafer-to-wafer bonding, a first die is bonded to a second die at a bonding interface. Various configurations of capacitors are placed along an inner portion of an edge seal of the bonded dies to detect a discontinuity in the bonding interface. These configurations include interdigitated capacitors, which can be horizontally or vertically oriented, parallel-digitated capacitors, and pillars forming a parameter around the dies with conductive portions offset from the pillar and extending inside the dies. Other configurations can be used.

A ferroelectric memory device includes an alternating stack of insulating layers and composite layers that are interlaced along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and an inner ferroelectric material layer including a first ferroelectric material, and a vertical stack of electrically-non-insulating material portions located between the inner ferroelectric material layer and the composite layers. Each of the composite layers includes a respective electrically conductive layer and a respective outer ferroelectric material layer including a second ferroelectric material, embedding the respective electrically conductive layer, and contacting a respective electrically-non-insulating material portion.

A memory device includes a first alternating stack including first insulating layers and first electrically conductive layers that are interlaced along a vertical direction, where a first stepped cavity located inside the first alternating stack includes a first stepped bottom surface containing horizontally-extending surface segments of the first electrically conductive layers, a memory opening vertically extending through each layer within the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements, a first insulating spacer contacting sidewalls of the first stepped cavity, and a first electrically conductive strip including a first horizontally-extending bottom strip segment contacting one of the first electrically conductive layers, a first horizontally-extending top strip segment that overlies a topmost layer within the first alternating stack, and a first vertically-extending strip segment connecting the first horizontally-extending bottom strip segment and the first horizontally-extending top strip segment.

A method of forming a staircase structure in a semiconductor device includes forming primary terrace patterns in an alternating stack, repeating a respective anisotropic etch process that etches unmasked portions of the alternating stack and a respective mask trimming process to form additional terrace patterns, determining if the respective mask trimming process trimmed the mask within a desired distance range using the primary terrace patterns in the staircase structure as alignment marks, and forming layer contact via structures which contact electrically conductive layers in the primary terrace patterns and the additional terrace patterns.

A memory apparatus includes memory cells configured to store a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means configured to detect whether data stored in a group of the memory cells as one bit per each of the memory cells has errors. The control means is also configured to bypass error correction of the data stored in the group of the memory cells in response to not detecting the errors in the data stored.