SANDISK TECHNOLOGIES LLC

Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Design and implementation of non-traditional logic gates or memory elements, often leveraging new materials or device physics to achieve multi-functionality, adaptive thresholds, or higher density.

Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.

Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.

Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Novel hardware designs and processing pipelines tailored for specific computational tasks, such as graphics rendering, neural network operations, or matrix transformations, often involving custom circuits, memory arrays, or data flow mechanisms.

Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.

Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.

Specialized hardware, architectural designs, and computational methods to improve the speed, efficiency, and security of artificial intelligence and machine learning model execution, particularly for inference and data processing.

Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.

Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.

Technologies for establishing and managing high-bandwidth, low-latency communication pathways between computing components, peripherals, or systems, focusing on signal integrity, synchronization, and interface standards.

Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.

Encompasses strategies and technologies to ensure the availability, integrity, and recoverability of data and systems, including robust backup, replication, error correction, and efficient data restoration.

Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.

Methods for depositing thin films with controlled conformality, thickness, and material properties, including selective deposition on specific areas, often using atomic layer deposition (ALD), chemical vapor deposition (CVD), or epitaxial growth.

Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.

Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.