SANKEN ELECTRIC CO., LTD.

The semiconductor device includes an n-type first semiconductor region 11 , and an n-type common contact region 12 formed locally with a high impurity concentration on the first semiconductor region 11 and connected to a common electrode that serves as both a first main electrode of a switching element and a protection element side first electrode on the protection element side. A p-type second semiconductor region 13 and an n-type third semiconductor region 14 are provided in a switching element region R 1 . The p-type second semiconductor region 13 is formed in the first semiconductor region 11 at a location separated in the radial direction from the common contact region 12 , and the n-type third semiconductor region 14 is formed in the second semiconductor region 13 . A second main electrode is connected to the third semiconductor region 14 . A p-type fourth semiconductor region 16 is provided in a protection element region R 2 . The p-type fourth semiconductor region 16 is formed in the first semiconductor region 11 at a location separated in the radial direction from the common contact region 12 . A protection element side second electrode is connected to the fourth semiconductor region 16.

This diode has an undoped GaN layer 11 , an Al x Ga 1-x N layer (0<x<1) 12 thereon, a Mg-doped p-type In y Ga 1-y N layer (0<y<1) 13 having an island-like shape thereon, a metal electrode 14 thereon, an anode electrode 15 which is provided on the Al x Ga 1-x N layer 12 and which is electrically connected to the metal electrode 14 and a cathode electrode 16 which is provided on a part of the Al x Ga 1-x N layer 12 which is located on the opposite side from the anode electrode 15 with respect to the p-type In y Ga 1-y N layer 13 . In this diode, at a non-operating time, a two-dimensional electron gas 17 is formed in the undoped GaN layer 11 in the vicinity part of a hetero-interface between the Al x Ga 1-x N layer 12 and the undoped GaN layer 11 except a part below the p-type In y Ga 1-y N layer 13.

A nitride-based semiconductor device includes a third nitride-based semiconductor layer having a two-dimensional hole gas layer. As viewed from a control electrode side, the third nitride-based semiconductor layer on a first main electrode side includes a recess, or includes multiple third nitride-based semiconductor layers intermittently provided on a second nitride-based semiconductor layer and each of the multiple third nitride-based semiconductor layers is electrically connected to the control electrode.

The semiconductor device includes an n-type first semiconductor region 11 formed on a surface side of a p-type semiconductor substrate 10 and serving as a common path for currents flowing through a switching element and a protection element, an n-type common contact region 12 formed on the first semiconductor region 11 with a high impurity concentration and connected to a common electrode 21 serving as both a first main electrode and a protection element side first electrode, a p-type second semiconductor region 13 and a p-type third semiconductor region 14 locally formed in the first semiconductor region 11 at locations separated from the common contact region 12 , and an n-type fourth semiconductor region 15 locally formed in the second semiconductor region 13 in plan view. A second main electrode 22 is connected to the fourth semiconductor region 15 , and a protection element side second electrode 26 is provided inside the third semiconductor region 14.

Provided is a semiconductor device, which includes: a drift region of a first conductivity type, a base region of a second conductivity type on the drift region, a source region of a first conductivity type on the base region, a gate electrode disposed on the base region via an insulating film, an auxiliary trench provided on the base region, and a polysilicon electrode of a first conductivity type, electrically connected to the base region and the source region, and provided in the auxiliary trench.

A semiconductor device according to one or more embodiments may include a high potential region electrically connected with an electrode of a high potential side, a low potential region electrically connected with an electrode of a low potential side, a breakdown voltage improvement region arranged between the high potential region and the low potential region, including a first semiconductor region, field plates, each of the field plates arranged facing a surface of the breakdown voltage improvement region interposed an insulating layer, the field plates coupled each other between the high potential region and the low potential region, and extending in a direction that intersects the array direction, an auxiliary semiconductor region locally arranged corresponding to at least one field plate selected from the field plates on the surface of the first semiconductor region, and a connection electrode connecting the auxiliary semiconductor region with field plate selected from the field plates.

A semiconductor device according to one or more embodiment may include: an IGBT region including a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type arranged on the first semiconductor region; a third semiconductor region of the first conductivity type arranged on the second semiconductor region; a fourth semiconductor region of the second conductivity type arranged on the first semiconductor region and opposite the second semiconductor region; and a control electrode that is arranged via an insulating film opposite the second semiconductor region; and a diode region comprising a fifth semiconductor region of the second conductivity type on the first semiconductor region. In the semiconductor device according to one or more embodiments, an impurity concentration of the fifth semiconductor region may be lower than the impurity concentration of the second semiconductor region.

A semiconductor device includes a semiconductor substrate which includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region, and in which in plan view, an element region in which a semiconductor element is formed and a termination region located closer to an end part side of the semiconductor substrate than the element region are formed. The semiconductor device includes multiple ditch structures formed in parallel in plan view in the termination region, penetrating from a top side through the second semiconductor region and reaching the first semiconductor region, with a conductive layer in a floating state formed inside, and a third semiconductor region of the first conductivity type having higher impurity concentration than the first semiconductor region provided at a bottom of the ditch structure.

A semiconductor device is disclosed including a sub-layer with first conductivity type, a drift layer with first conductivity type, a base region with second conductivity type positioned on the drift layer, a source region in contact with the base region, a source electrode, a plurality of trenches, at least one of the trenches in contact with the drift layer, the base region, and the source region, a plurality of insulating regions, at least one of the insulating regions positioned inside of each trench, a plurality of gate electrodes, at least one of the gate electrodes positioned inside of each trench; and a plurality of field plates, at least one of the field plates electrically connected to the source electrode and positioned in the insulating region in the trench. The field plate comprises high-resistance polysilicon.

A semiconductor device according to one or more embodiments is disclosed that may include a p-type first semiconductor region, an n-type second semiconductor region formed on a surface of the first semiconductor region, an n-type third semiconductor region formed by separating from the second semiconductor region, an n-type fourth semiconductor region having a higher impurity concentration than the second semiconductor region, an insulating film arranged on the semiconductor substrate, a gate electrode arranged via the insulating film between the second semiconductor region and the third semiconductor region, a first main electrode electrically connected to the second semiconductor region, a second main electrode electrically connected to the fourth semiconductor region, a p-type fifth semiconductor region on the third semiconductor region, which has a higher impurity concentration than that of the first semiconductor region, and an auxiliary electrode connected to the fifth semiconductor region.