SEIKO INSTRUMENTS INC.

Provided is a LOCOS offset MOS field-effect transistor in which a first lightly-doped N-type drain offset region with a LOCOS oxide film and a second lightly-doped N-type drain offset region without a LOCOS oxide film are formed in a drain-side offset region, and both the regions are covered with a gate electrode. Provision of the first lightly-doped N-type drain offset region mitigates an electric field applied to the first lightly-doped N-type drain offset region to increase a breakdown voltage. Provision of the second lightly-doped N-type drain offset region increases carriers within the second lightly-doped N-type drain offset region to obtain a high current drivability.

A liquid crystal color display device has a light shielding film formed on a color filter substrate at positions overlying TFT elements formed on a TFT substrate. A color filter provided on the color filter substrate has blue-colored and green-colored layers laminated on the light shielding film at regions corresponding to green display pixels, blue-colored and red-colored layers laminated on the light shielding film at regions corresponding to red display pixels, and a blue-colored layer formed on the light shielding film at regions corresponding to blue display pixels. The laminated colored layers reduce reflection of blacklight by the light shielding film onto the TFT elements to prevent leak current of the TFT elements thereby preventing deterioration of the display quality.

An automatic slicing apparatus reduces the likelihood of failure to make a sliced piece specimen even if continuously operated. The apparatus, on the basis of an exchange command signal, detaches a sample block attached to a cutting base and attaches a new sample block to the cutting base. The apparatus cuts a sliced piece of a predetermined thickness by moving a knife with respect to the sample block having been attached to the cutting base. The apparatus also observes the sliced piece having been cut and judges the sliced piece by comparing an observation data obtained by the observation means and a sample block cut face data. When the apparatus judges that the sliced piece is good, the apparatus transmits an exchange command signal.

To provide a voltage regulator having improved response characteristics in case of overshoot. The voltage regulator includes: a transistor ( 303 ) for detecting an overshoot at an output terminal; and a current mirror circuit connected to the transistor ( 303 ). If the transistor ( 303 ) detects the overshoot, a control transistor ( 16 ) is turned ON to discharge a voltage of the output terminal.

Provided are a charge and discharge control circuit capable of reducing a circuit size, and a battery device. In a charger reverse connection detection circuit ( 116 ), a comparison circuit or the like is not used, and two NMOS transistors are used, whereby circuit sizes of the reverse connection detection circuit ( 116 ) and a charge and discharge control circuit ( 110 ) are reduced. Accordingly, a consumption current is reduced, and a manufacturing cost is also reduced.

In a method of manufacturing a semiconductor device, a first film is formed directly on a semiconductor substrate and a second film is formed on the first film. A region of the second film is then etched to form an opening that exposes the first film. The first film is then arbitrarily patterned by etching to expose a surface of the semiconductor substrate. Thereafter, the second film and the exposed surface of the semiconductor substrate are simultaneously etched using the patterned first film as a mask and in an etching ambient having a low etching rate for the first film and having a high etching rate for the second film and the semiconductor substrate until the second film is almost completely etched and a detection amount of a monitored element of the first film increases.

There is provided a piezoelectric vibrator 1 that includes a base substrate 2 , a lid substrate 3 , a piezoelectric vibrating reed 4 , a pair of external electrodes 38 and 39 , a pair of through electrodes 32 and 33 , and routing electrodes 36 and 37 . The lid substrate 3 includes a recess 3 a for a cavity and is bonded to the base substrate so that the recess faces the base substrate. The piezoelectric vibrating reed 4 is bonded to the upper surface of the base substrate so as to be received in a cavity that is formed between both the substrates. The pair of external electrodes 38 and 39 is formed on the lower surface of the base substrate. The pair of through electrodes 32 and 33 is formed by hardening paste P, which contains a plurality of metal fine particles and a plurality of metal beads P 1 , so as to pass through the base substrate, maintains airtightness in the cavity, and is electrically connected to the pair of external electrodes, respectively. The routing electrodes 36 and 37 are formed on the upper surface of the base substrate and electrically connect the pair of through electrodes to the piezoelectric vibrating reed. The melting point of the metal bead is higher than the firing temperature of the paste.

[Task] A constant-modulus alloy, which has a low saturation magnetic flux density to provide weakly magnetic properties, a high Young's modulus, a low temperature coefficient of Young's modulus, and high hardness, is provided. A hairspring, a mechanical driving apparatus and a watch and clock, in which the alloy is used, are provided. [Means for Solution] The alloy consists essentially of, by atomic weight ratio, 20 to 40% Co and 7 to 22% Ni, with the total of Co and Ni being 42.0 to 49.5%, 5 to 13% Cr and 1 to 6% Mo, with the total of Cr and Mo being 13.5 to 16.0%, and with the balance being essentially Fe (with the proviso that Fe is present in an amount of 37% or more) and inevitable impurities. The alloy is heated to a temperature of 1100 degrees C. or higher and lower than the melting point, followed by cooling. The alloy is subsequently subjected to repeated wiredrawing and intermediate annealing at 800 to 950 degrees C., thereby forming a wire at a working ratio of 90% or more. The resultant wire has a fiber structure having a <111> fiber axis. The wire is subsequently cold rolled at a rolling reduction of 20% or more, thereby obtaining a sheet, followed by heating the sheet at a temperature of 580 to 700 degrees C. The obtained magnetically insensitive, highly hard, constant modulus alloy has a {110}<111> texture. 2500 to 3500 G of saturation flux density, (−5˜+5)×10 −5 degrees C −1 of temperature coefficient of Young's modulus as measured at 0 to 40 degrees C., and 350 to 550 of Vickers hardness

The present invention can rotationally drive a motor with main drive pulses corresponding to loads with the simple constitution without using a counter circuit. A control circuit, in driving a motor with a second main drive pulse, when a rotation detection signal which is indicative of the rotation of the motor is detected by a rotation detection circuit after a predetermined reference time elapses, continues rotational driving of the motor with the second main drive pulse, when the rotation detection signal is detected before the predetermined reference time elapses, changes the rotational driving of the motor with a first main drive pulse having a shorter pulse width than the second main drive pulse, and when the rotation detection signal is not detected, forcibly rotationally drives the motor with a correction drive pulse having a largest pulse width and, thereafter, rotationally drives the motor with the first main drive pulse.

Provided is a delay circuit that has a delay time period independent of a power supply voltage and has the equal delay time period between a case of a change in input signal from Low to High and a case of a change in input signal from High to Low. The delay time period is determined as a time period necessary for a voltage of a capacitor ( 17 ) (internal voltage (Va)) to increase from a ground voltage (VSS) to a voltage equal to or higher than an inverting threshold voltage of a constant current inverter ( 19 ) (threshold voltage (Vtn) of an NMOS transistor ( 16 )). Therefore, the delay time period is determined with reference to the ground voltage (VSS). Note that the same holds true for an internal delay circuit ( 20 ). If the input signal (Vin) becomes High, the delay circuit utilizes the delay time period caused by an internal delay circuit ( 10 ). On the other hand, if the input signal (Vin) becomes Low, the delay circuit utilizes the delay time period caused by the internal delay circuit ( 20 ). Those internal delay circuit ( 10 ) and internal delay circuit ( 20 ) are identical with each other.