SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.

A clock domain crossing queue structure is provided. The clock domain crossing queue structure used to perform a clock domain crossing data transmission includes a clock domain crossing First In First Out (FIFO) and a first generating module. The clock domain crossing First In First Out is located in a slow clock domain and configured to synchronize combined signals of a plurality of signals corresponding to a plurality of data entries processed in the slow clock domain to a fast clock domain. The slow clock domain is a slower clock cycle of a read clock cycle and a write clock cycle and the fast clock cycle domain is a faster clock cycle of the read clock cycle and the write clock cycle. The first generating module is located in the fast clock cycle and configured to generate a first flag signal.

A receiver circuit without baseline wandering is shown, in which the paired alternating (AC) coupling circuit and conductive (DC) coupling circuit are connected in parallel. The feedback voltages obtained from the DC coupling circuits are controlled to track the desired common mode voltage. In this manner, the common mode voltage between the equalization nodes is stable.

A static random-access memory (SRAM), a control method thereof and a computer software product capable of two-read and two-write (2R2W) operations in the same clock cycle are shown. The SRAM has first and second memory cells, whose write word lines are uniformly controlled for programming of consistent write data. The first read word line of the first memory cell and the second read word line of the second memory cell are controlled independently. A write address latch receives a first write address, to be fetched by the first write decoder as well as the second write decoder in response to the clock signal being at a high level. A write address register receives a second write address, to be fetched by the first write decoder as well as the second write decoder in response to the clock signal being at a low level.

A static random-access memory (SRAM), a control method thereof and a computer software product capable of two-read and one-write (2R1W) operations in the same clock cycle are shown. The SRAM has a pair of memory cells: the first memory cell and the second memory cell. Their write word lines are uniformly controlled for the programming of consistent write data. The first read word line of the first memory cell and the second read word line of the second memory cell are controlled independently. An I/O port is coupled to the first memory cell and the second memory cell to provide consistent write data and consistent inverse write data to both the first memory cell and the second memory cell, acquire first read data from the first memory cell, and acquire second read data from the second memory cell.

A processor operating a physical machine and a virtual machine is shown. The processor includes a virtualization hardware accelerator, which pre-caches whole instruction content, read from a virtual machine memory, of a target trigger instruction in a virtual machine control data structure, wherein the target trigger instruction is operative to trigger a virtual machine exit event and needs instruction emulation on the physical machine. A virtual machine hypervisor run by the physical machine in software obtains the instruction content of the target trigger instruction from the virtual machine control data structure, and performs instruction decoding and instruction emulation for the target trigger instruction based on the obtained instruction content.

A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

A computer system with a processor having an encryption and decryption engine is shown. The encryption and decryption engine includes a key table, which is provided for encryption and decryption of the system memory. In response to a platform setting instruction, the processor reads a key identification code from a key identification code register, and reads control parameters from a control parameter register. Based on the control parameters, the processor manages a key, associated with the key identification code, in the key table.

A processor with a high-capacity last-level cache is shown, which includes a plurality of cores, a primary storage node, a plurality of cache slices corresponding to the cores, and a mesh-type interconnection structure. The cache slices are combined as a last-level cache. The mesh-type interconnection structure connects the primary storage node and the cache slices in a ring, and connects at least two cache slices non-adjacent to each other in the ring.

A computer system with data encryption and decryption on system memory is shown. The computer system has a system memory storing data, and a processor coupled to the system memory. The processor has key registers storing multiple keys. Based on the access address on the system memory, the processor selects a target key from the key registers, to apply the target key to perform data encryption and decryption on the system memory.

A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.