SiFive, Inc.

Systems and methods are disclosed for data storage in a non-inclusive cache. For example, an integrated circuit may include a cache that includes a databank with multiple entries configured to store respective cache lines; and an array of cache tags, wherein each cache tag includes a data pointer that points to an entry in the databank. For example, methods may include allocating the entry in the databank to the cache including the array of cache tags from amongst multiple caches in the integrated circuit by writing the data pointer to the cache tag in the array of cache tags.

Described are methods, data structures, logic, and circuitry which enable a cache replacement policy to track a number of cache states greater than a number of ways in a cache. A cache replacement policy state structure provides that the number of cache states is greater than the N ways for each way per cache index in the cache The additional states can enable different handling and prioritization of data that has been prefetched (prefetch cache states) or loaded with a non-temporal hint from software (non-temporal cache states). The number of prefetcher states and non-temporal states are each less than the number of ways. The non-temporal states can only be promoted to certain of the cache states.

Systems and methods are disclosed for a configurable interconnect address remapper with event detection. For example, an integrated circuit can include a processor core configured to execute instructions. The processor core includes region registers defined by a From Address range and a To Address, a register storing a number of regions defined in the integrated circuit, interrupt enable registers associated with each pair of region registers, and event flags associated with each pair of region registers; an interconnection system handling transactions from the processor core; an interconnect address remapper translating an address associated with a transaction using the one or more pair of region registers; and an interrupt controller receiving an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one raised event flags when at least one of the one or more pair of region registers matches the transaction address.

Systems and methods are disclosed for error management in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a world identifier checker circuitry configured to check memory requests for one or more memory mapped resources that are received via the bus that have been tagged with a world identifier to determine whether to allow or reject access based on the tagged world identifier; a world identifier checker circuitry configured to compare the tagged world identifier to a world list for a resource that specifies which world identifiers supported by the integrated circuit are authorized for access to the resource; and a data store configured to store world error data, including the tagged world identifier of a memory request that has been rejected by the world identifier checker circuitry.

A method and apparatus for a cache coherency state request vector is described. A method includes selecting, by a first agent, one or more bits in a cache coherency state request vector, where a selected bit in the cache coherency state request vector indicates an acceptable cache coherency state for a cache block indicated in a request message, transmitting, by the first agent to a second agent, the request message for the cache block, the request message including the cache coherency state request vector, and receiving, by the first agent from the second agent, a response message with a cache coherency response state, wherein the cache coherency response state indicates a cache coherency state responsive to the cache coherency state request vector.

Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be mapped to a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be mapped to a physical register of the first set of physical registers.

Systems and methods are disclosed for logging guest physical address for memory access faults. For example, a method for logging guest physical address includes receiving a first address translation request from a processor pipeline at a translation lookaside buffer for a first guest virtual address; identifying a hit with a fault condition corresponding to the first guest virtual address; responsive to the fault condition, invoking a single-stage page table walk with the first guest virtual address to obtain a first guest physical address; and storing the first guest physical address with the first guest virtual address in a data store, wherein the data store is separate from an entry in the translation lookaside buffer that includes a tag that includes the first guest virtual address and data that includes a physical address.

Disclosed herein are systems and methods for processing masked memory accesses including handling fault exceptions and checking memory attributes of memory region(s) to be accessed. Implementations perform a two-level memory protection violation scheme for masked vector memory instructions. The first level memory check ignores mask information associated with a masked vector memory instruction and operates on a memory footprint associated with the masked vector memory instruction. If a memory protection violation is detected or speculative access is denied with respect to the memory footprint, a second level memory check evaluates mask information at a vector element level to determine whether a fault exception should be raised. If a mask bit for a vector element is set and a memory violation is detected, then a fault exception is raised for the masked vector memory instruction. If a mask bit is not set, execution of the masked vector memory instruction can continue.

A window-based constraint on issue order can be applied where a shared resource (e.g., a transfer buffer for load data) is allocated out-of-order by a first unit in a processor (e.g., a load/store unit) and freed in-order by a second unit in the processor (e.g., a unit that moves data out of the transfer buffer). The first unit can have a first issue queue and issue logic that imposes a constraint that an instruction that allocates the shared resource is only ready to issue if it is within or younger than a clearance window defined within the first issue queue, where the clearance window is defined to allow at least some out-of-order issue of instructions that allocate the shared resource.

Systems and methods for data storage in a non-inclusive cache. An integrated circuit includes a cache that includes a databank with multiple entries configured to store respective cache lines and an array of cache tags. Each cache tag includes a data pointer that points to an entry in the databank. A method includes allocating the entry in the databank to the cache including the array of cache tags from amongst multiple caches in the integrated circuit by writing the data pointer to the cache tag in the array of cache tags.