SiFive, Inc.

A system may generate an annotation based on an attribute determined in connection with logic. In some implementations, the logic may be between a first function (e.g., a first point of logic, such as an encoder) and a second function (e.g., a second point of logic, such as a decoder) in a first level circuit representation. The attribute may indicate, for example, fault protection using error correction code, parity, or Gray code, or a power level, frequency domain, or clock domain. The system may then identify circuitry in a second level circuit representation corresponding to the annotated logic in the first level circuit representation. The second level circuit representation may be generated based on the first level circuit representation. The system may then mark the identified circuitry in the second level circuit representation having the attribute. In some implementations, the system may determine a fault profile of an integrated circuit design based on the marking.

Disclosed are systems and methods that include accessing design parameters to configure an integrated circuit design. The integrated circuit design may include a transaction source or processing node to be included in an integrated circuit. The transaction source or processing node may be configured to transmit memory transactions to memory addresses. A compiler may compile the integrated circuit design with the transaction source or processing node to generate a design output. The design output may be configured to route memory transactions based on their targeting cacheable or non-cacheable memory addresses. The design output may be used to manufacture an integrated circuit.

The present application relates to generating a design for an integrated circuit, where the design includes a layer that can be enabled and/or disabled on demand. In an example, a system receives an input declaring a layer associated with a function. The system defines a first layer block of the layer, where corresponding code references the layer and is included in code of a first module. The system defines a second layer block of the layer, where corresponding code references the layer and is included in code of a second module. The system defines a first port for the first layer block, the first port referencing the layer and indicating that output of the first layer block is accessible to the second layer block conditioned on the layer being enabled. The system causes a compilation of the codes, where the compilation removes the first port from the circuit design.

Systems and methods are disclosed for integrated circuit design using integrated circuit shells. For example, a system may generate an integrated circuit core design expressed in a hardware description language. The integrated circuit core design may express circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC). The one or more functions may have connection points providing first inputs and outputs to the one or more functions. The system may query an integrated circuit shell expressed in a hardware description language. The integrated circuit shell may express circuitry that describes a limited set of pads to be implemented in the ASIC. The limited set of pads may provide second inputs and outputs to the integrated circuit. The query may determine availability of pads of the limited set of pads to connect to the connection points of the one or more functions.

The present application relates to generating a design for an integrated circuit. The integrated circuit can include state elements that store data and a protection component, such as an encoder or decoder, that enables detection and, possibly correction, of errors in the stored data. The integrated circuit can be designed using an integrated circuit generator that implements a hardware description language (HDL). In the HDL, code for the integrated circuit can be defined. This code can indicate that the data forms an atomic data group to be processed together and can declare this data as being protected by a particular protection type (e.g., error correction codes). An annotation referring to the data protection can be included in an operation defined in the code. Based on the declaration and the annotation in the code, a data structure can be generated and can indicate that the protection component is to be implemented.

Test verification code generation may be automated. Automating the generation of the test verification code may include generating an integrated circuit design for an integrated circuit that includes the object model and generating the verification code based on the object model. The object model is used by a parser to generate a verification code. The object model may include field values including a protection parameter field and a sequence field. The protection parameter field may include information that identifies node(s) that are associated with an intended protected region in the integrated circuit design and indicates characteristics of an encoding scheme applied in the intended protected region. The sequence field may include information representing a list of signals that can report an error. The verification code may be configured to inject the error during simulation of the integrated circuit design to verify that the system correctly responds to the error.

A first circuitry may have a first interface. A response circuitry having a system interface may connect to the first circuitry. The response circuitry may receive an input selection that determines an error handling mode used to respond to an error (e.g., in a lockstep system, the error could be a difference between an output at the first interface and a second output at a second interface identified by comparing the first output to the second output). In some implementations, the error handling mode may cause the response circuitry to provide the output to the system interface and send an indication to software based on detecting the error. In some implementations, the error handling mode may cause the response circuitry to contain at least a portion of the output by disabling at least a portion of the system interface for multiple clock cycles based on detecting the error.

A method for managing orders of operations between one or more clients and one or more servers is disclosed. The method includes partitioning addressable regions of logical servers on or within an interconnect link into multiple regions including a first orderable region, and providing logical client an ability to push ordering responsibility within the first orderable region to a server. Over the first orderable region, two request messages for access to memory-mapped sources including two respective operations are transmitted, and the two request messages originate from a same logical client. The ordering responsibility can include a first rule for order of operations between the two request messages.

An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The instance may include an input that is internal to the integrated circuit design. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. A parameter may be received indicating that the input should be exposed to a simulator. The IR data structure may be compiled to produce a register-transfer level (RTL) data structure. The RTL data structure may encode a logic description associated with the instance. The parameter may be used to permit a simulator to access a node in the RTL data structure that is associated with the input.

An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. A parameter comprising metadata associated with the instance may be received. A compiler may compile the IR data structure to produce a register-transfer level (RTL) data structure. The RTL data structure may encode a logic description associated with the instance. Compiling the IR data structure may include associating the parameter comprising metadata with the logic description.