SigmaStar Technology Ltd.

An image enhancement device includes a preprocessing circuit, an intelligent processor and a processor. The preprocessing circuit preprocesses input image data to generate first image data. The intelligence processor detects at least one region of interest in the first image data to generate at least one set of original region data, and enhances image quality of the at least one set of original region data to generate at least one set of enhanced region data. The processor mixes the at least one set of original region data and the at least one set of enhanced region data according to a blending ratio to generate at least one set of mixed region data, and replaces the at least one region of interest in the first image data with the at least one set of mixed region data to generate output image data.

A discrete cosine transform processing device includes an adder, a register, multiple multiply-accumulate operation circuits, an accumulator, an operation control circuit and an output circuit. The adder processes first input data based on a first permutation matrix to generate second input data. The register stores an operation matrix. The operation control circuit configures the multiply-accumulate operation circuits and the accumulator based on a matrix multiplication operation corresponding to a unit dimension, such that the operation matrix and the second input data are multiplied and accumulated by the multiply-accumulate operation circuits and the accumulator to generate a first operation result. The output circuit processes the first operation result based on a second permutation matrix to generate a second operation result, wherein the first permutation matrix, the operation matrix, and the second permutation matrix are derived from decomposition of a discrete cosine transform matrix.

A memory interface circuit is applied to an electronic device that includes a computing circuit and a memory. The memory interface circuit is coupled to the computing circuit and the memory and includes a command storage circuit, a state machine, and a memory control circuit. The command storage circuit is configured to store at least one command. The state machine is coupled to the command storage circuit and is configured to manage a current mode of the memory. The memory control circuit is coupled to the state machine and is configured to switch the current mode of the memory. The memory control circuit controls the memory to periodically operate in a first mode and a second mode, and the memory does not process the at least one command in the first mode.

An image processing device processes a frame using two buffer circuits and two direct memory access (DMA) circuits. The first buffer circuit comprises M buffer blocks, while the second contains W tiles. The DMA circuits operate in one of two modes. In the first mode, the first DMA writes a first pixel line into one of the M buffer blocks, and the second DMA reads N pixels from each buffer block, combining them to produce M×N pixels that are then written into one of the W tiles. In the second mode, the first DMA writes a second pixel line across the M buffer blocks, each block holding a segment of the line, and the second DMA reads M×N pixels from one buffer block and writes them into one of the W tiles. Once M lines have been written into the buffer blocks, the first DMA switches operation mode.

A controller outputs multiple different predetermined exposure control parameters to an image sensor during a first period after a device is powered on, such that the image sensor generates multiple sets of first frame data according to the predetermined exposure control parameters. An image processor generates multiple sets of statistical data based on the first frame data. A processor determines a first exposure control parameter according to the statistical data and outputs the first exposure control parameter to the image sensor via the controller, such that the image sensor generates second frame data according to the first exposure control parameter during a second period. A frame rate of each set of the first frame data is higher than that of the second frame data, and a resolution of each set of the first frame data is lower than that of the second frame data.

A data dimension expanding method includes the operations of: reading input tile data of input tensor data from a memory and storing the input tile data to a register of an intelligence processing unit; and copying the input tile data along a first dimension of the input tile data in the register according to a size of output tile data of output tensor data to generate first tile data, wherein a size of the first tile data is the same as the size of the output tile data, and the first tile data is utilized to perform an elementwise operation to generate the output tile data.

A chip is coupled to an external memory, a peripheral interface circuit, and a storage device. The storage device stores external memory information and multiple external memory initialization files. The chip includes an interface control circuit, a memory, and a computing circuit. The interface control circuit is configured to control the peripheral interface circuit. The computing circuit is configured to execute program codes and/or program instructions stored in the memory to perform the following steps: obtaining a value through the peripheral interface circuit; generating an index value based on the value; determining a target external memory initialization file from the external memory initialization files based on the index value and the external memory information; and loading an external memory parameter from the target external memory initialization file into the memory.

An intelligence processing unit (IPU) includes a memory, a grid processing circuit, and a convolution computation circuit. The memory is configured to store a part of a first input data of a deformable convolution operation, a part of a bias of the deformable convolution operation, a part of a weight of the deformable convolution operation, and a part of a grid, where the grid is transformed from an offset of the deformable convolution operation. The grid processing circuit is configured to perform a grid-sample operation to generate a second input data based on the first input data and the grid. The convolution computation circuit is configured to perform a convolution operation on the second input data, the weight, and the bias to generate an output data. The output data is substantially equal to the result of the deformable convolution operation.

A memory controller circuit includes a data buffer circuit, a data hold circuit and a control circuit. The data buffer circuit stores data read from a memory, which includes a plurality of memory banks and a plurality of channels corresponding to the memory banks. The data hold circuit is coupled to the plurality of channels. The control circuit is configured to, according to a memory bank ID from a data read command, control the data hold circuit to not enable a target channel corresponding to the memory bank ID and to hold target data on the target channel at the target channel when a storage capacity of the data buffer circuit is full, and control the data hold circuit to enable the target channel to read the target data on the target channel to the data buffer circuit when the storage capacity of the data buffer circuit is not full.

An image processing chip is coupled to an external memory and includes a processing circuit and an encoder. The processing circuit is configured to write data to be encoded into a memory address of the external memory. The encoder includes first and second registers, a data input circuit, and an encoding circuit. The first register is configured to store the memory address under control of the processing circuit. The data input circuit is configured to read the data to be encoded from the external memory according to the memory address in the first register and write the data to be encoded into the second register. The encoding circuit is configured to perform an encoding operation according to the data to be encoded in the second register to generate encoded data. The encoder stores the encoded data or an output data derived from the encoded data in the external memory.