Silicon Storage Technology, Inc.

A diode comprises a semiconductor substrate, an n-well formed in the semiconductor substrate, a p-well formed in the semiconductor substrate that is spaced apart from the n-well, a first isolation region formed in the n-well, a first electrode formed in direct contact with the n-well and formed of a metal material, a first heavily doped region formed in the n-well and having a dopant concentration greater than a dopant concentration of the n-well, a second electrode formed in direct contact with the first heavily doped region, a second isolation region formed in the semiconductor substrate and between the n-well and the p-well, a second heavily doped region formed in the p-well and having a dopant concentration greater than a dopant concentration of the p-well, and a third electrode formed in direct contact with the second heavily doped region.

A method of programming a memory cell having a floating gate by applying a first program pulse to the memory cell to place electrons on the floating gate, wherein the first program pulse comprises a program voltage that includes a preliminary voltage level in a first portion of the first program pulse and a first voltage level in a second portion of the first program pulse, wherein the first voltage level is greater than the preliminary voltage level. The first voltage level is applied immediately successive to the preliminary voltage level. Then, applying successive program pulses to the memory cell to place additional electrons on the floating gate, wherein the successive program pulses include the program voltage, and wherein the program voltage increases in voltage level for each one of the successive program pulses relative to a previous one of the successive program pulses or the first program pulse.

Examples for ultra-precise tuning of a selected memory cell are disclosed. In one example, a method of programming a first memory cell in a neural memory to a target value is disclosed, the method comprising programming a second memory cell by applying programming voltages to terminals of the second memory cell; and determining if an output of the first memory cell has reached the target value.

Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a system comprises an array of resistive random access memory (RRAM) units arranged in rows and columns; and a sense amplifier for determining a differential value stored in a first RRAM unit and a second RRAM unit in the array, wherein the first RRAM unit comprises a first select transistor coupled to a first set of one or more RRAM cells and the second RRAM unit comprises a second select transistor coupled to a second set of one or more RRAM cells.

In one example, a method comprises generating a first voltage; generating a second voltage; prior to a read operation, charging a first node and a third node to the first voltage and charging a second node and a fourth node to the second voltage, wherein a first capacitor couples the first node and the second node and a second capacitor couples the third node and the fourth node; and during the read operation, discharging the first node through a reference memory cell and discharging the third node through a selected memory cell, wherein the second node tracks the first node through the first capacitor and the fourth node tracks the second node through the second capacitor.

Numerous examples are disclosed of systems and methods for operating one or more arrays of resistive random access memory (RRAM) cells. In one example, a read bias generator comprises a bias transistor, a feedback loop, a replica resistor, and a reference unit. Optionally, the read bias generator is coupled to an array of RRAM units.

A memory device includes a SOI substrate comprising bulk silicon, an insulation layer vertically over the bulk silicon, and a silicon layer vertically over the insulation layer. A memory cell includes source and drain regions formed in the bulk silicon with a channel region of the bulk silicon extending therebetween, and a floating gate which includes a first portion of the silicon layer disposed vertically over and insulated from a first portion of the channel region by the insulation layer. The first portion of the silicon layer is epitaxially thickened or a layer of polysilicon is formed on the first portion of the silicon layer. A select gate is disposed vertically over and insulated from a second portion of the channel region. A control gate is disposed vertically over and insulated from the floating gate. An erase gate is disposed vertically over and insulated from the source region.

A first example comprises programming a memory cell to store a value; applying a series of currents of increasing size to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias. A second example comprises programming a memory cell to store a value; applying a predetermined current to a bit line of the memory cell; and measuring a voltage of a control gate terminal of the memory cell to determine a bias.

Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a method comprises adjusting a bias voltage applied to one or more non-volatile memory cells in an artificial neural network, performing a performance target check on the one or more non-volatile memory cells in the artificial neural network, and repeating the adjusting and performing until the performance target check indicates an electrical parameter is within a predetermined range.

Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives current from a W+ bit line and current from an associated W− bit line, and the output block generates an output signal that is a differential signal in certain embodiments and is a single ended signal in other embodiments.