Company patents
SILICONWARE PRECISION INDUSTRIES CO., LTD.
SILICONWARE PRECISION INDUST RIES CO., LT D. demonstrates a clear focus on core semiconductor technologies, with Semiconductor Packaging & Encapsulation (75.3% of portfolio) and Chip-to-Chip Interconnect (Bonding, Bumps) (60.5% of portfolio) being dominant. Surprisingly, despite its semiconductor core, the company shows an emerging focus in Optical Elements & Systems, which, while only 5.0% of its portfolio, experienced a significant 120.0% year-over-year growth in 2026 so far, indicating a strategic diversification into optical technologies.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
380 US filings (since 2023) · 9 categories · 21 themes
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.
The design and manufacturing of integrated circuits that combine optical and electronic components, particularly for high-speed data communication between processors and memory.
Design and manufacturing techniques for incorporating antenna structures directly into electronic devices, product housings, or materials, often under constraints of space, aesthetics, or environmental factors.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Techniques and structures used to reduce unwanted electromagnetic coupling, scattering, or interference between multiple antennas, different frequency bands, or sensitive electronic components within a device.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.
Techniques and apparatus for electrically testing semiconductor devices, integrated circuits, or wafers during manufacturing or post-assembly, including built-in self-test (BIST) and contact reliability assessment.
Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.
Antennas engineered to operate effectively across a wide continuous range of frequencies (broadband) or multiple distinct frequency bands, often requiring specific radiating element geometries or impedance matching circuits.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Systems and methods for electronically steering or shaping antenna beams by controlling the phase and amplitude of signals fed to individual elements in an array, including calibration techniques and multi-antenna configurations.
Patents
Showing 491-500 of 500