SILTRONIC AG

A method tests the stress robustness of a semiconductor substrate. The method includes: forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate or on a native oxide layer that is interposed on the surface; cooling the semiconductor substrate and the nitride layer; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas, which includes hydrogen or a hydrogen compound or both; processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800° C. and not more than 1300° C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property that is related to the formed dislocations.

A method produces wafers from a cylindrical ingot of semiconductor material having an axis and an indexing notch in an outer surface of the cylindrical ingot and parallel to the axis. The method includes, in the order specified: (a) simultaneous removal of a multiplicity of sliced wafers from the cylindrical ingot by multi-wire slicing in the presence of a cutting agent; (b) etching of the sliced wafers with an alkaline etchant in an etching bath at a temperature of 20° C. to 50° C. and for a residence time, such that the material removed from each of the sliced wafers is less than 5/1000 of an initial wafer thickness; and (c) grinding of the etched wafers by simultaneous double-disk grinding using an annular abrasive covering.

A characteristic thickness value of an edge of a wafer is determined, including at a notch position. The wafer is placed in a placement area, surrounded by a boundary, of susceptor for depositing an epitaxial layer. The characteristic thickness value at the notch position is checked to see if it differs by more than a percentage limit from the characteristic thickness value at an edge position having the greatest characteristic thickness value. The placing of the substrate wafer on the placement area is executed in such a way that a distance of the wafer from the boundary of the placement area is smaller at the edge position having the greatest characteristic thickness value or at the notch position than at other edge positions.

A heteroepitaxial wafer includes, in the following order: (1) a substrate made of silicon having a thickness, a diameter, a crystal orientation, a resistivity, a frontside, and a backside; (2) a nucleation layer comprising aluminium nitride (AlN) and 3C-SiC; (3) a first boron nitride layer having a first boron nitride layer thickness; and (4) a layer of nitride having a nitride layer thickness comprising an element out of the list of elements of aluminum, gallium, indium and thallium.

A method produces semiconductor wafers in a chamber of a deposition reactor of a plant. The method includes: repeatedly depositing an epitaxial layer on a substrate wafer in the chamber, producing semiconductor wafers, and at the same time: conditioning a replacement chamber outside the plant by purging the replacement chamber with a purge gas; interrupting the deposition of the epitaxial layer; replacing the chamber with the replacement chamber, after the conditioning, the replacement chamber being sealed and transported in a closed state to the plant or after the conditioning, the replacement chamber is transported to the plant and in this process purge gas is passed through the replacement chamber; and continuing the deposition of the epitaxial layer in the replacement chamber, producing a second number of semiconductor wafers.

A cover is used for a cleaning module, in which a semiconductor wafer is cleaned with a fluid in a vertically orientated state. The cover includes: a base having a wedge-like cross section; a sealing frame for the cover; a hood covering the base and having a slot for introducing the semiconductor wafer into the cleaning module; a panel displaceable over the base and over the slot; and a bracket secured to the hood so as to be displaceable over the slot. A first drainage channel is incorporated in an upper side face of the bracket parallel with the slot and along an edge border, which is close to the slot, of the bracket. A second drainage channel is incorporated in an upper side face of the panel parallel with the slot and along an edge border, which is close to the slot, of the panel.

A semiconductor single-crystal silicon, is produced from a silicon substrate wafer containing interstitial oxygen in a concentration of more than 5×10 16 AT/cm 3 (new ASTM) by an RTA treatment of the wafer in a first heat treatment at a first temperature in a temperature range of not less than 1200° C. and not more than 1260° C. for a period of not less than 5 s and not more than 30 s, where the front side of the substrate wafer is exposed to an atmosphere containing argon; a second heat treatment at a second temperature in a temperature range of not less than 1150° C. and not more than 1190° C. for a period of not less than 15 s and not more than 20 s, where the front side of the wafer is exposed to an argon and ammonia, atmosphere, and a third heat treatment at a third temperature in a temperature range of not less than 1160° C. and not more than 1190° C. for a period of not less than 20 s and not more than 30 s, where the front side of the wafer is exposed to an atmosphere containing argon.

Silicon single crystals having an oxygen concentration of greater than 2×10 17 at/cm 3 , a concentration of pinholes having a diameter of greater than 100 μm of less than 1.0×10 −5 l/cm 3 , a carbon concentration of less than 5.5×10 14 at/cm 3 , an iron concentration of less than 5.0×10 9 at/cm 3 , a COP concentration of fewer than 1000 defects/cm 3 , a LPIT concentration of fewer than 1 defect/cm 2 and a crystal diameter of greater than 200 mm, are produced by the Czochralski method employing a purge gas at specified pressures and flow rates.

A method cuts slices from workpieces using a wire saw with a wire array tensioned in a plane between two wire guide rollers supported between fixed and floating bearings. A workpiece is fed through the wire array perpendicular to a workpiece axis and the wire array plane. The workpiece is fed through the wire array while controlling a temperature of the workpiece with a cooling medium, with simultaneous axial movement of the floating bearings by adjusting a temperature of the fixed bearings in dependence on a depth of cut and in correlation with a first correction profile, and while simultaneously moving the workpiece along the workpiece axis in accordance with a specification of a second correction profile, which specifies a travel of the workpiece. The first correction profile and the second correction profile being opposed to a shape deviation.

Semiconductor wafers having a subsurface-referenced nanotopography of the upper side surface of less than 6 nm, expressed as a maximum peak-to-valley distance on a subsurface and referenced to subsurfaces with an area content of 25 mm×25 mm, are produced from a workpiece by feeding the workpiece through a wire web tensioned between wire guide rollers and divided into wire groups, the wires producing kerfs as the wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups is used to compensate movements of the wires of the wire group as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.