Company patents
Soitec
Soitec's patent strategy is heavily concentrated in Semiconductor Manufacturing Process, representing 56.8% of its portfolio, which saw a significant 36.8% YoY growth in 2024 before a decline in 2025 and so far in 2026. Surprisingly, while core semiconductor areas like Impedance Networks and Inorganic Devices showed rapid growth in 2024 (85.7% and 109.1% YoY respectively), the company appears to be shifting away from Integrated Circuit Layout & Arrangement and Transistor & Device Structure, both of which saw a 100.0% YoY decline in patenting activity so far in 2026.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
264 US filings (since 2023) · 11 categories · 22 themes
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Focuses on the design, fabrication, and application of piezoelectric materials and devices for sensing, actuation, or wave generation, including material properties, single crystal growth, and protective layers.
Devices utilizing piezoelectric materials to generate and filter acoustic waves, often for radio frequency applications, including surface acoustic wave (SAW) and bulk acoustic wave (BAW) structures.
Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Methods and structures for encapsulating, interconnecting, and integrating impedance network components, particularly acoustic filters, into larger modules or systems.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Methods and structures for mass-producing and assembling arrays of micro-LEDs onto a substrate, including transfer processes, bonding techniques, and defect management.
Development and optimization of the semiconductor material layers and their interfaces within an LED to control light emission properties, manage internal stress, and improve device efficiency.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.
Methods for depositing thin films with controlled conformality, thickness, and material properties, including selective deposition on specific areas, often using atomic layer deposition (ALD), chemical vapor deposition (CVD), or epitaxial growth.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Layout, material composition, and structural arrangement of photoelectric conversion elements and associated circuitry within image sensor arrays, including infrared detectors and back-side illuminated structures.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Patents
Showing 1-10 of 386