Space Exploration Technologies Corp.

Embodiments of the present disclosure are directed to techniques for autonomously transitioning a spacecraft from a power-saving state to a power-consuming state at a time after launch of the spacecraft on a launch vehicle. Because the spacecraft can autonomously detect conditions for transitioning to the power-consuming state, commands received via an umbilical connection to the launch vehicle, or detecting the presence or absence of such a connection, is unnecessary, thereby removing several technical barriers to eliminating such umbilical connections altogether. In some embodiments, low-cost vacuum detection devices that use very small amounts of power may be used by the spacecraft to detect when the spacecraft has reached an altitude suitable for transitioning to the power-consuming state.

In some embodiments, an antenna module includes an antenna element having a first side and a second side opposite the first side, the first side comprising a radiating side of the antenna element and a support structure disposed at the second side of the antenna element and configured to define a cavity, the support structure including a portion configured to reduce signal leakage between the antenna element and the cavity.

A phased array antenna system configured for communication with a satellite that emits or receives radio frequency (RF) signals travels in a first direction, the antenna system includes a phased array antenna including a plurality of antenna elements distributed in a plurality of M columns oriented in the first direction and a plurality of N rows extending in a second direction normal to the first direction, and a plurality of fixed phase shifters aligned for phase offsets between antenna elements in the first direction and a gain-enhancement system configured for gain enhancement in the second direction of radio frequency signals received by and emitted from the phased array antenna.

An example system can include a first antenna having a first orientation, a second antenna having a second orientation and a control system communicating with the first antenna and the second antenna. The control system performs operations which can include determining a pathway of a satellite, comparing the pathway to a first radiation pattern of the first antenna and a second radiation pattern of the second antenna, wherein the first antenna and the second antenna are each positioned such that a first keyhole of the first antenna does not overlap a second keyhole of the second antenna, to yield a comparison and selecting, based on the comparison, one of the first antenna or the second antenna to communicate with the satellite along the pathway.

An example system can include a first antenna having a first orientation, a second antenna having a second orientation and a control system communicating with the first antenna and the second antenna. The control system performs operations which can include determining a pathway of a satellite, comparing the pathway to a first radiation pattern of the first antenna and a second radiation pattern of the second antenna, wherein the first antenna and the second antenna are each positioned such that a first keyhole of the first antenna does not overlap a second keyhole of the second antenna, to yield a comparison and selecting, based on the comparison, one of the first antenna or the second antenna to communicate with the satellite along the pathway.

In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

An antenna calibration system for a phased array antenna in accordance with one embodiment of the present disclosure generally includes: a beamformer lattice including at least first and second beamformers, each corresponding to a subset of antenna cells, and each including a calibration section for comparing a reference signal to a non-reference signal; and a calibration antenna within the subset of antenna cells corresponding with the first beamformer, wherein the calibration antenna is configured to deliver a first reference signal (mTx) from the first beamformer to be received by a first operating antenna for comparison with a first non-reference signal (Rx) in the first beamformer or in the second beamfomer, and/or wherein the calibration antenna is configured to deliver a second non-reference signal (Tx) from a second operating antenna for comparison with a second reference signal (mRx) in the first beamformer or in the second beamformer.

In some embodiments, a phased array antenna, includes a plurality of antenna modules arranged in an antenna lattice configuration to form the phased array antenna, wherein an antenna module of the plurality of antenna modules includes an antenna element packaged together with an amplifier.

In an embodiment, an apparatus includes a source device including a first current limiter and a second current limiter in parallel with each other and a first transformer and a second transformer; a load device includes a third transformer and a fourth transformer in parallel with each other; and an Ethernet cable is electrically coupled between the source device and the load device, the Ethernet cable including first twisted pair lines and second twisted pair lines. A direct current (DC) voltage is provided to the first current limiter and the second current limiter, the first transformer is electrically coupled to an output of the first current limiter, and the second transformer is electrically coupled to an output of the second current limiter. The DC voltage is transmitted to the third transformer and the fourth transformer in parallel with each other via the first twisted pair lines and the second twisted pair lines. The first twisted pair lines and second twisted pair lines are included in an Ethernet cable electrically coupled between the source device and the load device.

In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.