Company patents
STATS ChipPAC Pte. Ltd.
STATS ChipPAC Pte. Ltd. maintains a strong focus on core semiconductor technologies, with Semiconductor Packaging & Encapsulation (76.6% of portfolio) and Semiconductor Manufacturing Process (69.7% of portfolio) showing consistent, albeit modest, growth in 2024-2025. Surprisingly, while Antennas has seen a steady decline in patenting activity (YoY -20.0% in 2024, -25.0% in 2025), there's an emerging focus on Welding & Soldering, which saw a remarkable 400.0% YoY growth so far in 2026, indicating a potential shift in manufacturing process innovation.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
389 US filings (since 2023) · 11 categories · 21 themes
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.
Design and manufacturing techniques for incorporating antenna structures directly into electronic devices, product housings, or materials, often under constraints of space, aesthetics, or environmental factors.
Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Specialized welding or bonding techniques and apparatuses tailored for joining small-scale electronic components, integrated circuits, or semiconductor wafers, emphasizing precision, miniaturization, and electrical connectivity.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Innovations in the design, materials, and manufacturing of lithography masks, including reflective masks, programmable masks, and defect mitigation strategies, to enable finer feature patterning and process control.
Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.
Methods and equipment for applying photoresist uniformly onto wafers, forming patterns through various exposure techniques (e.g., direct imaging, multi-exposure), and integrating patterned layers into semiconductor structures or packaging.
Techniques and structures used to reduce unwanted electromagnetic coupling, scattering, or interference between multiple antennas, different frequency bands, or sensitive electronic components within a device.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Methods and materials used to construct robust and protective enclosures for electronic devices, focusing on structural integrity, impact resistance, thermal dissipation, and specialized material properties for enhanced durability.
Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.
Techniques and systems utilizing laser beams for precise material modification, including cutting, cladding, ablation, and surface treatment, often for joining, shaping, or removing material.
Patents
Showing 1-10 of 457