Company patents
SUMCO Corporation
SUMCO Corporation's patent strategy reveals a surprising shift away from core semiconductor manufacturing, with its largest category, Semiconductor Manufacturing Process (39.4% of portfolio), experiencing a significant decline of 30.0% in 2025 and an 81.0% drop so far in 2026. This is further emphasized by the complete cessation of patenting in Transistor & Device Structure and Integrated Circuit Layout & Arrangement in 2025 and 2026, indicating a potential re-evaluation of its direct involvement in device-level innovation.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
216 US filings (since 2023) · 10 categories · 23 themes
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Methods and apparatus for cleaning polishing pads, dressers, chamber components, or finished substrates to remove residues, debris, or contaminants, often involving specialized nozzles, fluids, or mechanical actions.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Methods for producing glass-ceramic articles through controlled nucleation and crystallization processes, often involving specific thermal treatments to achieve desired microstructures and properties like strength or dimensional stability.
Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.
Methods for depositing thin films with controlled conformality, thickness, and material properties, including selective deposition on specific areas, often using atomic layer deposition (ALD), chemical vapor deposition (CVD), or epitaxial growth.
Integration of robotics, sensors, and control systems to automate the grinding, polishing, or deburring process, including workpiece handling, tool adjustment, and system maintenance for improved efficiency and precision.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Utilizing optical systems, cameras, and image processing algorithms for precise measurement of physical dimensions, alignment, defects, and features on semiconductor wafers or packages.
Techniques and devices for measuring, monitoring, and controlling the surface topography, film thickness, or other characteristics of a workpiece during or after grinding/polishing to achieve specific finish requirements.
Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.
Novel glass formulations, often doped with rare-earth elements or specific metal oxides, designed to achieve desired optical properties such as refractive index, light transmittance, polarization, or amplification.
Processes involving chemical and mechanical forces to planarize surfaces (CMP) or wet chemical treatments for cleaning, etching, or material removal, often utilizing specialized compositions, nozzles, or fluid management systems.
Techniques and systems for real-time or near-real-time measurement and adjustment of semiconductor manufacturing parameters (e.g., temperature, etch rate, ion beam uniformity) to ensure process quality and consistency.
Systems that employ imaging and image processing to automatically detect defects, verify states, or ensure quality control in manufactured goods, printed materials, or industrial processes.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Focuses on the chemical and physical properties of polishing slurries and the design of polishing pads, including their material composition, groove patterns, and thermal characteristics, to optimize chemical-mechanical planarization processes.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Design and application of abrasive tools and deburring heads tailored for specific geometries, materials, or access constraints, including flexible, expandable, or multi-component designs for precision finishing.
Design and manufacturing of multi-pane glass units with an evacuated gap and specialized sealing technologies to provide superior thermal insulation for architectural or appliance applications.
Glass articles treated with ion exchange or other chemical processes to induce a surface compressive stress layer, enhancing mechanical strength, scratch resistance, and impact toughness.
Patents
Showing 1-9 of 9
Gate Stack & Dielectric Engineering