UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.

A method for forming a first impurity region 3 connected to lower portions of first semiconductor pillars and second impurity regions 4 a and 4 b connected to lower portions of second semiconductor pillars includes forming a semiconductor layer 100 having an impurity concentration lower than an impurity concentration of each of the first impurity region 3 and the second impurity regions 4 a and 4 b in impurity boundary regions of the first impurity region 3 and the second impurity regions 4 a and 4 b in a vertical direction and a horizontal direction.

A memory device includes a page made up of plural memory cells arranged in a column on a substrate, and a page write operation is performed to hold positive hole groups generated by an impact ionization phenomenon, in a channel semiconductor layer by controlling voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each memory cell contained in the page and a page erase operation is performed to remove the positive hole groups out of the channel semiconductor layer by controlling voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity region, and the second impurity region. The first impurity layer of the memory cell is connected with a source line, the second impurity layer is connected with a bit line, one of the first gate conductor layer and the second gate conductor layer is connected with a word line, and another is connected with a drive control line, and the bit line is connected to a sense amplifier circuit via a switch circuit. During a page read operation, page data of a memory cell group selected by the word line is read into a sense amplifier circuit concurrently with a memory cell refresh operation for forming positive hole groups.

An N + layer and a P + layer that are impurity regions at a bottom portion are formed using as etching masks top first mask material layers and SiN layers surrounding Si pillars and formed in a self-aligned manner with respect to the Si pillars and a SiO2 layer. Then, a SiO2 layer is formed that has an upper surface located at the level of the bottom portions of the N + layer and the P + layer. Then, a W layer is selectively formed on exposed side faces of the N + layer and the P + layer. Then, a contact hole for connection to a wire metal layer is formed above the W layer as seen in plan view.

A first block in which a plurality of dynamic flash memory cells are arrange in a matrix shape on a substrate includes a first dynamic flash memory cell and a second dynamic flash memory cell. A second block disposed relative to the first block in a perpendicular direction or a parallel direction of the substrate includes a third dynamic flash memory cell and a fourth dynamic flash memory cell. Thus, dynamic flash memory cells are formed.

A dynamic flash memory cell includes an Si base material formed of a first channel region and a second channel region. In the Si base material, a first gate insulating layer surrounds the first channel region, and a second gate insulating layer surrounds the second channel region. A first gate conductor layer surrounds the first gate insulating layer, and a second gate conductor layer surrounds the second gate insulating layer. The first gate conductor layer is connected to a plate line PL, and the second gate conductor layer is connected to a word line WL. An N + layers formed, respectively, on one ends of the Si base materials are connected to a source line, and an N + layers formed, respectively, on the other ends of the Si base materials are connected to a bit line BL.

Provided is a memory semiconductor device including an access transistor, in which an n-type semiconductor layer is formed on a p-type semiconductor region provided on a substrate; a first p-type semiconductor layer that has a columnar shape exists in a vertical direction from a portion of the n-type semiconductor layer; an insulating layer that covers a portion of the first p-type semiconductor layer and a portion of the n-type semiconductor layer exists; in contact therewith, a first gate insulating layer contacts the first p-type semiconductor layer; in contact with the first gate insulating layer, a first gate conductive layer exists; a second p-type semiconductor layer whose surface is recessed exists on the first p-type semiconductor layer; a second gate insulating layer and a second gate conductive layer exist thereabove; and an n+ layer is provided on both sides thereof.

Provided is a semiconductor memory device that stores data by accumulating multiple carriers in an electrically floating body of a metal-oxide-semiconductor field-effect transistor. A plate line capacitively-coupled to the floating body is routed parallel to a word line in an isolated fashion for every word line so that, by applying voltage to the plate line, the multiple carriers are collectively erased along the word line. A writing operation of the semiconductor memory device is executed by causing sense amplifier circuits to read and latch data from cells along a selected word line, isolating bit lines from the sense amplifier circuits to erase data from the cells by applying voltage to the plate line belonging to the word line while simultaneously writing data into the sense amplifier circuits from the outside, and injecting multiple carriers into the bodies of the cells according to the states of the sense amplifier circuits.

P + layers which entirely cover top parts of Si pillars and which surround the Si pillars at equal widths in a plan view are formed by self-alignment with the Si pillars, W layers are formed on the P + layers, a band-shaped contact hole which is in contact with respective partial regions of the W layers and which extends in the Y direction is formed, and a supply wiring metal layer is formed by filling the band-shaped contact hole. The partial regions of the W layers are shaped so as to protrude to outside of the band-shaped contact hole in a plan view.

On P layer bases extending in a band shape in a first direction in plan view, N + layers also extending in a band shape in the first direction and Si pillars are formed. Subsequently, a gate insulating layer and gate conductor layers are formed so as to surround the Si pillars. Subsequently, contact holes whose bottom portions are in contact with the N + layers are formed in an insulating layer, and first conductor W layers are formed at the bottom portions of the contact holes. Subsequently, insulating layers each having a hole are formed in the contact holes. Subsequently, a second conductor W layer is formed in a second direction perpendicular to the first direction so as to be connected to the gate conductor layers.

A semiconductor element memory device includes a first block including first memory cells arranged in a matrix, and/or a second block including second memory cells each formed of two memory cells. The memory device is configured to perform a data hold operation of controlling voltages to be applied to plate lines, word lines, a source line, odd-numbered bit lines, and even-numbered bit lines to hold, in a semiconductor base, a positive hole group generated by an impact ionization phenomenon or a gate-induced drain leakage current, and a data erase operation of controlling voltages to be applied to the plate lines, the word lines, the source line, the odd-numbered bit lines, and the even-numbered bit lines to discharge the positive hole group from the semiconductor base. The number of first blocks and the number of second blocks are variable in the memory device that is in operation.