UNITED MICROELECTRONICS CORP.

Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.

Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.

Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.

Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.

Design and fabrication techniques for magnetoresistive random-access memory (MRAM) cells, focusing on magnetic tunnel junction (MTJ) stack profiles, electrode configurations, and dielectric encapsulation to improve performance and reliability.

Focuses on the physical design, materials, and manufacturing processes for individual memory cells, including transistor structures, interconnects, and multi-layered (3D) architectures to enhance density and performance.

Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.

Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.

Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.

Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.

Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.

Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.

Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.

Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.

Methods and equipment for applying photoresist uniformly onto wafers, forming patterns through various exposure techniques (e.g., direct imaging, multi-exposure), and integrating patterned layers into semiconductor structures or packaging.

Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.

Innovations in the design, materials, and manufacturing of lithography masks, including reflective masks, programmable masks, and defect mitigation strategies, to enable finer feature patterning and process control.

Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.

Design and implementation of non-traditional logic gates or memory elements, often leveraging new materials or device physics to achieve multi-functionality, adaptive thresholds, or higher density.

Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.

Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.

Techniques for precise material removal, pattern shaping, and controlling etch selectivity or uniformity, often involving plasma, wet chemistry, or directed beams to achieve desired features on semiconductor substrates.

Techniques and apparatus for measuring critical dimensions, overlay accuracy, defect detection, and surface topography in lithographic processes, often involving optical, laser, or charged particle beams.

Layout, material composition, and structural arrangement of photoelectric conversion elements and associated circuitry within image sensor arrays, including infrared detectors and back-side illuminated structures.

Hardware and control techniques for optimizing memory access latency, ensuring data integrity, and managing storage resources efficiently. This includes error correction, read/write voltage control, and intelligent data placement or in-memory computation.

Combining different types of functional chiplets (e.g., compute, memory, I/O, optical, power, biological) into a single package or system, often to optimize performance, power, or cost by leveraging specialized components.

Focuses on the design, fabrication, and application of piezoelectric materials and devices for sensing, actuation, or wave generation, including material properties, single crystal growth, and protective layers.

Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.

Design and operation of analog and mixed-signal circuits within the memory array, such as page buffers, sense amplifiers, and data latches, responsible for reading and writing data from/to memory cells.

Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.

Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.

Processes involving chemical and mechanical forces to planarize surfaces (CMP) or wet chemical treatments for cleaning, etching, or material removal, often utilizing specialized compositions, nozzles, or fluid management systems.

Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.

Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.

Integrated circuits or sub-circuits designed to regulate, balance, or protect power delivery within a device, often involving specific transistor and capacitor arrangements.

Design and integration of thermoelectric modules for converting heat into electricity (power generation) or using electricity for cooling/heating, often involving p-type/n-type semiconductor pellets and waste heat recovery.

Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.

Methods and circuits for detecting and mitigating defects, ensuring data integrity, and enabling self-testing and repair mechanisms within memory devices and subsystems.