United Semiconductor (Xiamen) Co., Ltd.

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.

A manufacturing method of a semiconductor device includes following steps. A semiconductor substrate including a first portion located within a low voltage device region and a second portion located within a middle voltage device region is provided. A first pad oxide pattern and a second pad oxide pattern are formed above the first portion and the second portion, respectively. A first trench isolation structure and a second trench isolation structure are formed. At least a part of the first trench isolation structure is formed in the first portion and located adjacent to the first pad oxide pattern. At least a part of the second trench isolation structure is formed in the second portion and located adjacent to the second pad oxide pattern. An etching process is performed, and the second pad oxide pattern and a part of the second trench isolation structure are removed concurrently by the etching process.

A semiconductor structure includes a semiconductor wafer having integrated circuit die regions and a scribe lane between the integrated circuit die regions. A first monitor structure is disposed in the scribe lane. The first monitor structure is composed of consecutive n layers of MOM capacitors disposed in multiple metal layers.

A fabricating method of a gate dielectric layer of a high voltage transistor includes providing a semiconductor substrate. Then, a first insulating block and a second insulating block are formed to be embedded in the semiconductor substrate. Later, an insulating layer is formed to be disposed between the first insulating block and the second insulating block. The first insulating block has a first sidewall and a second sidewall. The second sidewall contacts the insulating layer. The first sidewall and the second sidewall are opposite. The first sidewall has a protruding portion. The second sidewall is perpendicular to the top surface of the semiconductor substrate and there is no turning point on the second sidewall.

A one transistor-two RRAM structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a first source/drain doped region embedded in the substrate at one side of the transistor. A first source/drain plug, a first metal line, a first plug, a second metal line, a second lower plug, a second RRAM and a second upper metal line are stacked from bottom to top in listed sequence. The first source/drain plug contacts the first source/drain doped region. A first lower plug, a first RRAM and a first upper metal line are stacked from bottom to top in listed sequence. The first lower plug contacts the first metal line.

A fabricating method of low voltage, middle voltage and high voltage transistors includes providing a substrate. A first active region, a second active region and a third active region are respectively disposed in a low voltage region, a middle voltage region and a high voltage region. Two second source/drain regions is embedded in the second active region. Two third source/drain regions are disposed in the third active region. A middle voltage gate dielectric material layer is formed to cover the first active region, the second active region and the two third source/drain regions. Later, a patterned mask is formed to expose all the middle voltage gate dielectric material layer disposed in the first active region, on the two second source/drain regions, and on the two third source/drain regions. Next, the exposed middle voltage gate dielectric material layer is removed completely by taking the patterned mask as a mask.

A method for aligning to a pattern on a wafer includes the steps of obtaining a plurality of first inline images from a plurality of first sample wafers, obtaining a first contour pattern of an alignment mark pattern from the plurality of first inline images, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

A method for fabricating a semiconductor device includes steps as follows. A gate structure is formed on a substrate. A fluorine-containing dopant is implanted into the substrate to form two lightly doped drain regions at two sides of the gate structure. A thermal treatment process is performed, in which a part of fluorine atoms of the fluorine-containing dopant diffuse onto a surface of the substrate. The part of fluorine atoms are removed.

A method for fabricating a semiconductor structure is disclosed. A substrate having a dielectric layer thereon and a gate trench formed in the dielectric layer is prepared. The substrate is subjected to a physical vapor deposition (PVD) process in a physical vapor deposition chamber equipped with an auto capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and on an interior surface of the gate trench. The PVD process comprises: (i) tuning the auto capacitance tuner to provide positive radio frequency (RF) bias to the substrate in the PVD chamber for a first time period; and (ii) subsequently tuning the auto capacitance tuner to provide negative RF bias to the substrate in the PVD chamber for a second time period.

The present invention provides a semiconductor device and a method of fabricating the same, which includes a substrate, a gate structure, and a dielectric layer. The gate structure is disposed on the substrate and includes an inverted trapezoidal shape. The dielectric layer is disposed on the substrate, and the gate structure is disposed within the dielectric layer. The gate structure includes a metal gate structure or a polysilicon gate structure.