Ventana Micro Systems Inc.

Each load/store queue entry holds a load/store physical address proxy (PAP) for use as a proxy for a load/store physical memory line address (PMLA). The load/store PAP comprises a set index and a way that uniquely identifies an L2 cache entry holding a memory line at the load/store PMLA when an L1 cache provides the load/store PAP during the load/store instruction execution. The microprocessor removes a line at a removal PMLA from an L2 entry, forms a removal PAP as a proxy for the removal PMLA that comprises a set index and a way, snoops the load/store queue with the removal PAP to determine whether the removal PAP is being used as a proxy for the removal PMLA, fills the removed entry with a line at a fill PMLA, and prevents the removal PAP from being used as a proxy for the removal PMLA and the fill PMLA concurrently.

A power management system with differentiated power scaling including multiple activity monitors and a differentiated power manager. Each activity monitor counts performance benefit estimation events of each of multiple devices to determine performance benefit estimate values, each being a measure of relative power utilization efficiency of a corresponding device. The differentiated power manager periodically evaluates the performance benefit estimate values and dynamically adjusts relative power provided to each device to achieve differentiated power scaling based on the performance benefit estimate values. Additional power available during a higher performance mode may be distributed only to those devices with higher performance benefit estimate values. During any mode of operation, the power provided to those devices with lower performance benefit estimate values may be redirected to those devices with higher performance benefit estimate values. Power may thus be distributed in an unequal manner to benefit those devices operating at higher efficiency.

An out-of-order and speculative execution microprocessor that mitigates side channel attacks includes a cache memory and fill request generation logic that generates a request to fill the cache memory with a cache line implicated by a memory address that misses in the cache memory. At least one execution pipeline receives first and second load operations, detects a condition in which the first load generates a need for an architectural exception, the second load misses in the cache memory, and the second load is newer in program order than the first load, and prevents state of the cache memory from being affected by the miss of the second load by inhibiting the fill request generation logic from generating a fill request for the second load or by canceling the fill request for the second load if the fill request generation logic has already generated the fill request for the second load.

A system and method for a cache memory subsystem including a first-level cache (L1) and an N-way set associative second-level cache (L2) inclusive of L1, including receiving a physical memory line address (PMLA) for allocation into L2, using a set index of the PMLA to select a set of N ways of L2, for each way of the selected set of N ways, forming a physical address proxy (PAP) for the PMLA, in which each formed PAP includes the set index portion and the corresponding way that uniquely identifies a corresponding one of the selected set of N ways of L2, for each of the N formed PAPs, receiving a corresponding indicator of whether the formed PAP is resident in L1, and selecting one of the selected N ways of L2 having a corresponding indicator indicating that the corresponding one of the N formed PAPs is not resident in L1.

A microprocessor includes a prediction unit (PRU) comprising a fetch block (FBlk) predictor (FBP) that predicts a sequence of FBlks, each FBlk having a corresponding fetch block start address (FBSA), and branch predictors; a macro-op (MOP) cache (MOC) includes MOC entries (MEs) including multi-FBlk MOC entries (MF-MEs) for holding MOPs decoded from instructions of multiple FBlks. The PRU detects a hit of a current FBSA on an MF-ME; performs a set of actions K times: looking up the current FBSA in the FBP and branch predictors to obtain outputs, using the outputs to predict a successor FBSA of a successor FBlk; and making the current FBSA the successor FBSA; and predicts that an FBSA of a successor FBlk to the MF-ME is the current FBSA resulting from performing K times the set of actions. K is a number of FBlks built into the MF-ME (alternatively times a loop unroll factor).

A microprocessor includes a macro-op (MOP) cache (MOC) that holds MOC entries (MEs), including single-fetch block MEs (SF-MEs) and multi-fetch block MEs (MF-MEs), comprising MOPs decoded from architectural instructions. A prediction circuit generates fetch block (FBlk) start addresses (FBSAs) to make predictions of a sequence of FBlks fetched from an instruction cache and MEs fetched from the MOC. A back end detects that execution of a MOP of an MF-ME needs an abort and generates an abort request. A control circuit flushes all the MF-ME's MOPs and signals the prediction circuit to restart prediction at the MF-ME's FBSA. For each current FBSA of N current FBSAs used to make N predictions starting with the FBSA of the MF-ME, the prediction circuit ignores a hit on any MF-ME and instead, if the current FBSA hits on an SF-ME, predicts the SF-ME, and otherwise predicts a FBlk at the current FBSA.

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), a decode unit, and a fusion engine. Each ME indicates whether it is a single-FBlk ME (SF-ME) that holds MOPs associated with a single FBlk whose architectural instructions have been decoded into the MOPs of the SF-ME or a multi-FBlk ME (ME-ME) that holds MOPs associated with multiple FBlks whose architectural instructions have been decoded into the MOPs of the MF-ME. For each FBlk of one or more FBlks in the program instruction stream: the decode unit decodes the architectural instructions of the FBlk into MOPs, and the fusion engine builds a SF-ME in the MOC using the decoded MOPs, and the fusion engine builds a MF-ME in the MOC using the MOPs of a series of SF-MEs.

A microprocessor includes a prediction unit (PRU) that continuously predicts a sequence of fetch block start addresses (FBSAs) that specify a corresponding sequence of fetch blocks (FBlks) in a program instruction stream and a macro-op cache (MOC) having MOC entries (MEs). The PRU installs into the MOC a loop body ME using a first FBSA value that specifies the loop body ME, instructs a fusion engine to build an unrolled loop multi-FBlk ME (ULP-MF-ME) using F copies of the loop body ME, installs the ULP-MF-ME using the same first FBSA value, detects a multiple-hit in the MOC on both the loop body ME and the ULP-MF-ME, and instructs a fetch unit to fetch from the MOC a number of copies of the ULP-MF-ME equal to an unrolled loop iteration count of the ULP-MF-ME and instructs the fetch unit to fetch the loop body ME until the loop exits.

A microprocessor includes a prediction unit (PRU) that predicts a sequence of fetch blocks (FBlks) in a program instruction stream, a macro-op (MOP) cache (MOC) that comprises MOC entries (MEs), and a fusion engine. A FBlk comprises a sequential run of architectural instructions. An ME holds MOPs into which architectural instructions of one or more FBlks are decoded and includes training fields, updated by the PRU as the PRU predicts the ME in the program instruction stream. The PRU, in response to detecting that the training fields of an ME indicate the ME has been a loop body ME that has exhibited a consistent loop iteration count within the program instruction stream, requests the fusion engine to use F copies of the MOPs of the loop body ME to build in the MOC an unrolled loop multi-FBlk ME; F is at least two.

A microprocessor includes a physically-indexed physically-tagged second-level set-associative cache. A set index and a way uniquely identifies each entry. A load/store unit, during store/load instruction execution: detects that a first and second portions of store/load data are to be written/read to/from different first and second lines of memory specified by first and second store physical memory line addresses, writes to a store/load queue entry first and second store physical address proxies (PAPs) for first and second store physical memory line addresses (and all the store data in store execution case). The first and second store PAPs comprise respective set indexes and ways that uniquely identifies respective entries of the second-level cache that holds respective copies of the respective first and second lines of memory. The entries of the store queue are absent storage for holding the first and second store physical memory line addresses.