Wenzhou University

A method for improving ability of strong PUF to resist machine learning attacks. When obfuscating challenge, method comprises: performing conversion on Rubik's cube matrix on basis of current challenge to generate cryptographic matrix, and constructing challenge matrix based on current challenge; determining matrix multiplication pattern of cryptographic matrix and challenge matrix on basis of cryptographic matrix, multiplying cryptographic matrix by challenge matrix to obtain obfuscation matrix, converting elements in obfuscation matrix to 0 or 1 according to parity of elements to obtain cryptographic challenge matrix; extracting elements in cryptographic challenge matrix to form cryptographic challenge, if PUF response generated currently is first PUF response of PUF response sequence, Rubik's cube matrix that generates cryptographic challenge in current obfuscation is randomly generated; if not, Rubik's cube matrix that generates cryptographic challenge in current obfuscation is cryptographic matrix generated by previous obfuscation.

A strong PUF circuit with good stability and anti-ML attack capacity is provided. The strong PUF circuit includes n delay modules, n−1 interconnection modules, an arbiter array and an XOR gate, wherein n is an integer greater than or equal to 1, each delay module is implemented based on a bias source structure, and the number of transmission paths of input signals can be increased by means of the characteristics of the bias source structure of the delay module to realize a diversity of transmission, thus realizing a highly complex and unpredictable challenge-response mapping relation without multiple strong PUFs. The transmission characteristics (transmission paths) of the input signals can be further obfuscated by means of the interconnection modules. Only one XOR gate is used for generating response outputs to further improve the stability.

An SPUF based on combinational logic and scan chain comprises an external stimulus source, a combinational logic circuit module, a scan chain circuit module, a data processing module and n switch circuits SW 0 , SW 1 , . . . , SWn− 1 , n=2m, and m is an integer greater than or equal to 1; combinational logic circuit module comprises n switch circuits S 0 , S 1 , . . . , Sn− 1 and a combinational logic circuit; the scan chain circuit module comprises n scan flip-flops (SFFs) SFF 0 , SFF 1 , . . . , SFFn− 1 ; each of the n switch circuits SW 0 , SW 1 , . . . , SWn− 1 and the n switch circuits S 0 , S 1 , . . . , Sn− 1 is implemented by a 2-to-1 multiplexer. The SPUF based on combinational logic and scan chain has high uniqueness and randomness, requires a few clock frequency changes, and has high reliability, more bits of responses and high security.

A timing-violation software physical unclonable function circuit including combinatorial logic pipeline architecture is provided. The combinatorial logic pipeline architecture serves as a hardware platform. The combinatorial logic pipeline architecture includes an arithmetic operation cell, and the arithmetic operation cell includes a carry lookahead adder for performing add operations. The timing-violation software physical unclonable function circuit generates PUF response outputs by triggering timing violations in the combinatorial logic pipeline architecture.

A device encrypted authentication method based on a strong physical unclonable function is disclosed, including: generating β matrixes formed by random transformation of a ┌√{square root over (b)}┐-order unit matrix, such that unnecessary device expenditure is reduced; when a sensing device is identified, information to be synchronized between the sensing device and a back-end server is transmitted in the registration phase, such that an attacker cannot obtain confidential information in the encryption phase, and the attacker cannot traverse or completely crack all these possible combinations in a short time; even if the attacker intercepts some CRPs, it is scarcely possible that data sent by the sensing device matches the CRPs collected by the attacker, and with the increase of the number b of bits of challenges and the quick convergence to 0, the accuracy of random guessing is only 50%.

A device encrypted authentication method based on a strong physical unclonable function is disclosed, including: generating β matrixes formed by random transformation of a ┌√{square root over (b)}┐-order unit matrix, such that unnecessary device expenditure is reduced; when a sensing device is identified, information to be synchronized between the sensing device and a back-end server is transmitted in the registration phase, such that an attacker cannot obtain confidential information in the encryption phase, and the attacker cannot traverse or completely crack all these possible combinations in a short time; even if the attacker intercepts some CRPs, it is scarcely possible that data sent by the sensing device matches the CRPs collected by the attacker, and with the increase of the number b of bits of challenges and the quick convergence to 0, the accuracy of random guessing is only 50%.

The invention discloses a challenge screening method for improving the stability of a strong Physical Unclonable Function (PUF). If the stability of the group of challenges (GOCs) is quantized by 1 or 0, the GOCs are defined as stable challenges or unstable challenges respectively; the GOCs and the stability of corresponding responses are defined as a challenge-stability pair (CSP); a machining learning training dataset is constructed through CSPs for obtaining a screening model, to associate the challenge stability with the screening model; during actual application of the strong PUF, the challenge stability of a strong PUF is determined through the screening model, and stable challenges of the strong PUF are screened out to form a stable challenge set, which is input into the strong PUF to extract identity information. The challenge screening method can effectively improve the stability of various strong PUFs and has better effect with external disturbance increasing.

The invention discloses a challenge screening method for improving the stability of a strong Physical Unclonable Function (PUF). If the stability of the group of challenges (GOCs) is quantized by 1 or 0, the GOCs are defined as stable challenges or unstable challenges respectively; the GOCs and the stability of corresponding responses are defined as a challenge-stability pair (CSP); a machining learning training dataset is constructed through CSPs for obtaining a screening model, to associate the challenge stability with the screening model; during actual application of the strong PUF, the challenge stability of a strong PUF is determined through the screening model, and stable challenges of the strong PUF are screened out to form a stable challenge set, which is input into the strong PUF to extract identity information. The challenge screening method can effectively improve the stability of various strong PUFs and has better effect with external disturbance increasing.

Disclosed is a software PUF based on an RISC-V processor for IoT security. A 32-bit RISC-V processor is used to generate abnormal information results in an abnormal operating state under a low voltage, and the abnormal information results are used to represent the features of the 32-bit RISC-V processor; 5-bit binary data obtained by comparing the abnormal information results with normal information results has high randomness and uniqueness and it is extremely difficult to directly extract internal abnormal information result from a hardware circuit of the 32-bit RISC-V processor, so modeling attacks based on the 5-bit binary data calculated according to the abnormal information results of the 32-bit RISC-V processor are almost impossible; in addition, when the 32-bit RISC-V processor is in an abnormal operating state, the operating frequency of the 32-bit RISC-V processor is dynamically adjusted through a frequency compensation method.

An SPUF based on combinational logic and scan chain comprises an external stimulus source, a combinational logic circuit module, a scan chain circuit module, a data processing module and n switch circuits SW0, SW1, . . . , SWn-1, n=2m, and m is an integer greater than or equal to 1; combinational logic circuit module comprises n switch circuits S0, S1, . . . , Sn-1 and a combinational logic circuit; the scan chain circuit module comprises n scan flip-flops (SFFs) SFF0, SFF1, . . . , SFFn-1; each of the n switch circuits SW0, SW1, . . . , SWn-1 and the n switch circuits S0, S1, . . . , Sn-1 is implemented by a 2-to-1 multiplexer. The SPUF based on combinational logic and scan chain has high uniqueness and randomness, requires a few clock frequency changes, and has high reliability, more bits of responses and high security.