Winbond Electronics Corp.

A semiconductor memory device and a test method thereof are provided. The semiconductor memory device includes a plurality of word lines, a row decoder, a first voltage pump circuit, a first programmable current comparator and a control circuit. The row decoder decodes a row address data and accordingly selects a test word line to be electrically connected to a first test path. The first voltage pump circuit is configured on the first test path and applies a test voltage to the test word line. The first programmable current comparator compares a test current flowing through the first test path with a programmable reference current to provide a test result signal. The control circuit uses the word lines as the test word line sequentially, compares the corresponding test current with the programmable reference current and determines whether the test word line is defective according to the test result signal.

A memory device and a data erasing method are provided. The data erasing method includes: dividing a memory block into a plurality of memory cell divisions; performing a first data erasing operation on the memory cell divisions; starting from a first memory cell division, performing a first erasing verification operation on each of the memory cell divisions one by one according to a first sequence and recording a first failure memory cell division; starting from a N th memory cell division, performing a second erasing verification operation on each of the memory cell divisions one by one according to a second sequence and recording a second failure memory cell division; and performing a second data erasing operation on at least one selected memory cell division between the first failure memory cell division and the second failure memory cell division.

A flash memory apparatus and an erasing method thereof are provided. The erasing method includes the following steps: applying an erase voltage to a target memory block among memory blocks; performing a first erase verification on the target memory block using a first erase verification voltage; performing a second erase verification on the target memory block using a second erase verification voltage higher than the first erase verification voltage in a case that a memory cell group failing the first erase verification is in the target memory block; and setting a first erase flag and a second erase flag corresponding to each memory cell group in the target memory block according to verification results of the first erase verification and the second erase verification to classify each memory cell group and accordingly adjust increase amount of the erase voltage.

Provided are a dynamic random access memory and a method for manufacturing the same. The DRAM includes: a plurality of word line structures, located in a substrate; a plurality of bit line structures, located above the substrate, crossing over the plurality of word line structures; a plurality of node contacts, each of which being located between adjacent two of the word line structures and adjacent two of the bit line structures; and a plurality of first spacers, separating the plurality of node contacts. Each of the plurality of first spacers further comprises: spacer material, filled in a gap between the node contacts that are adjacent; and a first cap layer, embedded in the spacer material.

The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.

A flash memory device and a programming method thereof are provided. The programming method includes: selecting a target memory area to be performed a programming operation from a plurality of memory areas, wherein the target memory area is divided into a plurality of memory cell groups; performing a programming verification on the target memory area; and in a case where the target memory area fails the programming verification, setting a programming time period of one of the memory cell groups to overlap with a programming time period of another one of the memory cell groups, and sequentially programming the memory cell groups accordingly.

A three-dimensional (3D) flash memory device is provided. The 3D flash memory device includes a substrate, a T-shaped polysilicon pillar, a select line pillar, a bit line pillar, first and second control gates, first and second floating gates, and first and second high-k dielectric pillars. The select line pillar and the bit line pillar are vertically disposed adjacent to first opposite sidewalls of the horizontally protruding portion on the substrate. The first control gate and the second control gate are positioned adjacent to second opposite sidewalls of the horizontally protruding portion. The first and second floating gates are laterally disposed between the horizontally protruding portion and the first and second control gates. The first and second high-k dielectric pillars are laterally disposed between the first floating gate and the first control gate, as well as between the second floating gate and the second control gate.

A memory device, a current-to-voltage converter, and a data line pre-charge method are provided. The current-to-voltage converter includes a first pre-charge circuit, a second pre-charge circuit, and a pull-down circuit. The first pre-charge circuit is configured to pre-charge a voltage on a data line to a preset voltage according to a sensing enable signal at a first logic level during a pre-charge period of a data sensing operation; The second pre-charge circuit is configured to generate a feedback voltage according to the voltage on the data line and pull up the voltage on the data line according to the feedback voltage during the pre-charge period. The pull-down circuit is configured to discharge the data line according to the sensing enable signal at a second logic level.

Provided is a memory device, including a first bit line, a first word line, a second bit line, a second word line, a sensing amplifier circuit, and a voltage supply circuit. The first bit line and the second bit line are respectively coupled to a first memory cell and a second memory cell. The second bit line is complementary to the first bit line. The sensing amplifier circuit includes a first transistor and a second transistor. The first transistor and the second transistor are coupled in series between the first bit line and the second bit line. The sensing amplifier circuit includes a first node located between the first bit line and the second bit line. The voltage supply circuit is coupled to the sensing amplifier circuit.

Provided are a flash memory and a manufacturing method thereof. The flash memory includes a substrate, a first gate device, first doped regions, a first spacer, a capping layer, a hardmask layer, first contacts, a first protective layer, a second protective layer, a second gate device, second doped regions and a second spacer. The first protective layer is disposed between the first contacts and the hard mask layer, the capping layer and the first spacer. The second protective layer is disposed between the first protective layer and the first contacts, the capping layer, the first spacer and the substrate. The second gate device is disposed on the substrate in the peripheral region. The second doped regions are disposed in the substrate on two sides of the second gate device. The second spacer is disposed on the sidewall of the second gate device.