Company patents
Wolfspeed, Inc.
WOLFSPEED INC. shows a surprising shift in its patent strategy, with significant declines across nearly all categories in 2025 and so far in 2026, including a -88.6% drop in its largest category, Transistor & Device Structure (31.7% of portfolio), and a -76.9% decline in Semiconductor Packaging & Encapsulation (30.7% of portfolio) in 2026. This contrasts sharply with strong growth in Semiconductor Manufacturing Process (YoY +73.9% in 2024, +22.5% in 2025) and the emergence of Semiconductor Diodes & Transistors with 69 patents in 2025, suggesting a re-prioritization towards core manufacturing and specific device types despite an overall portfolio slowdown.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
508 US filings (since 2023) · 12 categories · 33 themes
Development and manufacturing of semiconductor devices using wide bandgap materials like Silicon Carbide (SiC) or Gallium Nitride (GaN) for high-power, high-frequency, or high-temperature applications.
Techniques and methodologies for fabricating semiconductor devices, including etching, deposition, annealing, isolation, and doping steps, aimed at improving yield, performance, or enabling new structures.
Advanced techniques for forming and optimizing gate dielectrics, work function layers, and other dielectric layers within transistor structures to improve performance, reliability, and scaling.
Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.
Focuses on the design and manufacturing of transistors where the gate material fully encircles the channel, often using nanosheets or fins, to improve electrostatic control and reduce short-channel effects.
Novel materials and processes for forming low-resistance electrical contacts and interconnects within semiconductor devices, including selective deposition, silicidation, and barrier layers for improved performance and scaling.
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Incorporation of novel semiconductor, dielectric, or metallic materials into transistor structures to achieve enhanced performance, new functionalities, or specific device characteristics.
Design and assembly of power conversion, distribution, and protection modules, focusing on compact form factors, efficient electrical connections, and robust protective measures for electronic systems, often in high-power applications.
Integrated solutions for dissipating heat generated by high-density semiconductor devices within the package, including embedded cooling structures, cold plates, and optimized fluidic channels.
Packaging technologies where bare dies are embedded within a mold compound or substrate cavity, and then interconnected using redistribution layers (RDLs) for fan-out or compact integration, often avoiding through-silicon vias in the chips themselves.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Circuit designs and control techniques focused on maximizing the power conversion efficiency of amplifiers, especially for radio frequency (RF) or audio applications, often involving load modulation, envelope tracking, or specific amplifier classes (e.g., Class-D, Doherty).
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Novel electrical connection methods within or between package components, including through-glass vias (TGVs), backside contacts, and optimized redistribution layers for improved signal and power integrity.
Development of novel materials and designs for bonding, sealing, and underfill applications, focusing on improving mechanical integrity, electrical performance, and preventing defects like cracks or delamination in chip-to-chip connections.
Inspection and testing methods specifically designed for wafers before, during, or after bonding processes, including verification of bonding surfaces, alignment, and defect detection in multi-wafer or stacked die assemblies.
Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.
Focuses on novel circuit configurations for DC-DC, DC-AC, or AC-DC conversion, often involving resonant operation, multi-level structures, or switched capacitors to improve efficiency, power density, or voltage conversion ratios.
Systems and methods for automated substrate transport, precise positioning, temperature regulation, and chamber environment management to ensure process stability, uniformity, and yield in semiconductor manufacturing.
Integration of various sensor types (e.g., thermal, strain) or display components directly onto semiconductor substrates or within device architectures for compact and high-performance systems.
Development and application of resin compositions, molding compounds, and underfill materials to protect semiconductor devices from environmental factors, moisture, mechanical stress, and for structural integrity.
Techniques and systems utilizing laser beams for precise material modification, including cutting, cladding, ablation, and surface treatment, often for joining, shaping, or removing material.
Techniques and systems for precisely measuring electrical or electromagnetic properties of materials or components, often involving specialized resonators, waveguides, or multi-range measurement systems to ensure accuracy.
Processes involving chemical and mechanical forces to planarize surfaces (CMP) or wet chemical treatments for cleaning, etching, or material removal, often utilizing specialized compositions, nozzles, or fluid management systems.
Amplifier designs that allow for dynamic adjustment of their operating characteristics, such as gain, impedance, or amplification path, based on control signals, input conditions, or desired performance modes.
Utilizing optical systems, cameras, and image processing algorithms for precise measurement of physical dimensions, alignment, defects, and features on semiconductor wafers or packages.
Techniques for designing and fabricating the conductive pathways (interconnects) and their contacts between different components within an integrated circuit, focusing on density, reliability, and performance.
Materials and processes for hermetic encapsulation, conformal coating, optical chip sealing, and stretchable conductors for electronic and optoelectronic devices.
Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.
Methods and circuits to detect and compensate for various imperfections in amplifier operation, such as DC offset, gain errors, phase errors, duty-cycle errors, or input error components, to improve accuracy and signal integrity.
Patents
Showing 1-10 of 72
Advanced Electronic Packaging