Wuhan BOE Optoelectronics Technology Co., Ltd.

A driving circuit structure, an array substrate, a display device, and a method for preparing the array substrate are provided. The driving circuit structure includes: a base substrate; an initial signal line on the base substrate; a clock signal line on the base substrate; and a first insulating layer on a side of the initial signal line away from the base substrate and including a first via. The initial signal line is connected to the clock signal line through the first via.

The present disclosure provides an array substrate and a preparation method therefor, and a display panel. The array substrate includes a plurality of pixel pairs distributed in an array, where two gate lines are provided between two adjacent rows of pixel pairs, and each the pixel pair includes a first pixel electrode and a second pixel electrode arranged side by side and connected to the same data line, a first pixel switch and a second pixel switch electrically connected with the first pixel electrode and the second pixel electrode, respectively, in an extension direction of the data line, the first pixel switch and the second pixel switch being distributed in pairs between two different pixel pairs, respectively, and a first pixel switch and a second pixel switch corresponding to a pixel pair being located at both sides of the pixel pair, and a first conductive structure.

An array substrate and a display device are provided. The array substrate includes a base substrate, and a first electrode layer, a plurality of first signal lines, and a plurality of second signal lines on the base substrate, the first signal lines are arranged in a first direction, the second signal lines are arranged in a second direction; the first electrode layer includes a plurality of first electrodes arranged in an array in the first direction and the second direction, a connection portion is provided between adjacent two first electrodes on two sides of a same first signal line, and the connection portion is configured to connect the two first electrodes; and the connection portion is closer to the second signal line relative to a straight line that passes through a central region of the first electrode and extends in the first direction.

An array substrate, a driving method thereof, and a display device. In the array substrate, rows of sub-pixels include groups of sub-pixels, each group of sub-pixels includes part of the rows of sub-pixels, and charging times of the part of the rows of sub-pixels are overlapped. A charging time of the second part of the plurality of rows of sub-pixels is longer than a charging time of the first part of the plurality of rows of sub-pixels. During a first time period, a same data signal is written into the first part of the plurality of rows of sub-pixels and the second part of the plurality of rows of sub-pixels, and during a second time period, a data signal written into the second part of the plurality of rows of sub-pixels is at least partially the same as the data signal written during the first time period.

The present disclosure provides an array substrate and a preparation method therefor, and a display panel. The array substrate includes a plurality of pixel pairs distributed in an array, where two gate lines are provided between two adjacent rows of pixel pairs, and each the pixel pair includes a first pixel electrode and a second pixel electrode arranged side by side and connected to the same data line, a first pixel switch and a second pixel switch electrically connected with the first pixel electrode and the second pixel electrode, respectively, in an extension direction of the data line, the first pixel switch and the second pixel switch being distributed in pairs between two different pixel pairs, respectively, and a first pixel switch and a second pixel switch corresponding to a pixel pair being located at both sides of the pixel pair, and a first conductive structure.

Provided is a display substrate, including: a base substrate; a gate driving circuit; first signal lines in a side region, a first corner region and a second corner region. The first signal lines include an initiation signal line and an initiation signal lead on a side of the initiation signal line close to the gate driving circuit, and the two extend in a second direction and are electrically connected through a first connecting line in the second corner region. First signal lines are provided with an anti-static structure in at least one of first position and second position, the first position includes a connection between the initiation signal line, initiation signal lead and the first connecting line, and the second position includes a portion of the first signal lines on a side of a row where a first-stage shift register unit is located close to the binding opposite region.

A display panel and a display device are provided. The display panel includes: an opposite substrate and a display substrate arranged opposite to each other, and multiple support pillars between the opposite substrate and the display substrate. The display substrate includes a display area and a non-display area surrounding the display area. The non-display area includes a first wiring area. The multiple support pillars include first support pillars in the display area and second support pillars in the non-display area. Partial support pillars corresponding to the first wiring area among the second support pillars extend in a direction perpendicular to an extending direction of the side edge of the first wiring area.

A display substrate includes a display area and a non-display area surrounding the display area. The non-display area includes a fan-shaped area between the display area and a side edge of the display substrate. The fan-shaped area includes: multiple first wiring lines extending along a direction parallel to an extending direction of the side edge, and multiple second wiring lines extending along a direction perpendicular to the extending direction. The multiple first wiring lines and the multiple second wiring lines are interconnected to form multiple grid units. In each grid unit, a first distance between two first wiring lines and a second distance between two second wiring lines are both less than a preset value.

A display substrate is provided, including: a base substrate; a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer and a passivation layer sequentially arranged on the base substrate along a direction away from the base substrate; and a first electrode via hole penetrating the passivation layer. The second conductive layer, includes a first electrode. The second conductive layer includes a gate electrode. The third conductive layer includes a transfer portion, of which an orthographic projection on the base substrate falls within an orthographic projection of the first electrode on the base. An opening area of the first electrode via hole gradually decreases in a direction pointing towards the base substrate, and an exposed part of the transfer portion by the first electrode via hole serves as a part of a via hole sidewall of the first electrode via hole.

An array substrate ( 10 ) includes: a base plate; gate lines ( 11 ), data lines ( 12 ), and pixel units, all on the base plate, wherein each pixel unit includes a display electrode ( 13 ) having at least one electrode portion ( 131 ), each electrode portion ( 131 ) includes a main chain electrode ( 1311 ) and branch chain electrodes ( 1312 ) all electrically connected to the main chain electrode ( 1311 ); and a black matrix layer ( 14 ) on a side of the pixel units distal to the base plate, wherein the black matrix layer ( 14 ) includes openings ( 141 ) and a light shielding portion ( 142 ). On the base plate, an orthogonal projection of each opening ( 141 ) covers orthogonal projections of the branch chain electrodes ( 1312 ) of one corresponding display electrode ( 13 ), and an orthogonal projection of the light shielding portion ( 142 ) covers orthogonal projections of the gate lines ( 11 ), the data lines ( 12 ) and the main chain electrode ( 1311 ).