Company patents
X-Celeprint Limited
X-Celeprint Limited's patent strategy reveals a strong, albeit fluctuating, focus on core semiconductor technologies, with Semiconductor Manufacturing Process making up 28.0% of its portfolio. While categories like Inorganic Devices (Thermoelectric, Piezo) saw a significant 200.0% YoY growth in 2024, the overall trend for most semiconductor categories shows a notable decline in patenting activity so far in 2026, with several categories like Chip-to-Chip Interconnect (Bonding, Bumps) and Multi-Chip & 3D Assemblies having 0 patents filed this year, suggesting a potential shift in R&D priorities or a slowdown in patenting for these areas.
Patent Trend by Technology Area
Yearly patent publications since 2023
Product themes
Product-level themes inferred from filings since 2023, with category chips showing where each theme appears. Select a theme to filter the patents below.
75 US filings (since 2023) · 12 categories · 16 themes
Methods and structures for mass-producing and assembling arrays of micro-LEDs onto a substrate, including transfer processes, bonding techniques, and defect management.
Methods and structures for integrating and enclosing electronic components into compact, multi-functional modules, often involving embedded components, multi-layer substrates, and electromagnetic shielding for performance and miniaturization.
Methods for temporarily attaching a wafer or substrate to a carrier for thinning, dicing, or other processing, followed by controlled debonding, often using light-sensitive resins, temporary adhesives, or roughened interfaces.
Focuses on the design, fabrication, and application of piezoelectric materials and devices for sensing, actuation, or wave generation, including material properties, single crystal growth, and protective layers.
Manufacturing processes and material compositions for creating electronic circuits on flexible or conformable substrates, enabling novel form factors, enhanced durability, and new applications beyond rigid PCBs.
Methods and structures for encapsulating, interconnecting, and integrating impedance network components, particularly acoustic filters, into larger modules or systems.
Focuses on the physical construction and integration of electronic components, such as antennas, IC chips, and display elements, into smart cards or secure documents, often involving multi-layer structures and specialized materials.
Devices utilizing piezoelectric materials to generate and filter acoustic waves, often for radio frequency applications, including surface acoustic wave (SAW) and bulk acoustic wave (BAW) structures.
Techniques for stacking multiple semiconductor dies or active layers vertically to achieve higher density and shorter interconnections, often utilizing through-silicon vias (TSVs) or other vertical conductive paths like through-hole electrodes.
Structural innovations in individual transistors, such as fin-based field-effect transistors (FinFETs), 3D gate structures, or multi-layer active regions, aimed at improving performance or density.
Design and operation of transistors optimized for memory applications, including floating body devices, ferroelectric FETs (FeFETs), vertical TFTs for 3D arrays, and charge-trapping memory cells.
Techniques and structures used to reduce unwanted electromagnetic coupling, scattering, or interference between multiple antennas, different frequency bands, or sensitive electronic components within a device.
Design and manufacturing techniques for incorporating antenna structures directly into electronic devices, product housings, or materials, often under constraints of space, aesthetics, or environmental factors.
Development of memory cells utilizing resistive switching or phase-change materials, including novel material compositions, multi-layered structures, and integration with selector devices like bipolar junction transistors, to achieve non-volatile storage.
Manufacturing processes and structural designs for transistors utilizing fin-shaped channels or multiple gates (e.g., FinFETs, Gate-All-Around FETs) to enhance gate control and reduce short-channel effects.
Techniques for forming electrical contacts, vias, and interconnects to semiconductor devices, including advanced methods like contact-over-active-gate (COAG) and backside contacts for improved density and performance.
Patents
Showing 1-10 of 15
Integrated Filter Packaging