Xiamen Tianma Micro-Electronics Co., Ltd.

The present disclosure discloses a display device. The display device includes a first display structure, a second display structure and a backlight device. The first display structure includes first pixels arranged in an array, the first pixels are divided into multiple dimming areas, and each dimming area includes at least one first pixel. The first display structure is for adjusting the transmittance of each dimming area for lights emitted by the backlight device according to an image to be displayed in the next frame of the second display structure.

Disclosed are a display panel and a display device. The display panel includes a pixel circuit. In the pixel circuit, a reset device includes a first sub-transistor and a second sub-transistor, and a connection node between the first sub-transistor and the second sub-transistor is a second node; a compensation device includes a third sub-transistor and a fourth sub-transistor, a connection node between the third sub-transistor and the fourth sub-transistor is a third node; the pixel circuit includes a second capacitor and a third capacitor; two pole plates of the second capacitor are respectively connected to a line of first scan signal and the second node; two pole plates of the third capacitor are respectively connected to a line of second scan signal and the third node; and the second capacitor (C 2 ) and the third capacitor (C 3 ) satisfy: C 2 ≤C 3.

Provided are an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: a substrate, a first active layer of a first thin film transistor, a first insulating layer, a first metal layer, and a second active layer of a second thin film transistor. The first metal layer includes a first connection portion, which overlaps one of a source contact region or a drain contact region of the first active layer and overlaps one of a source contact region or a drain contact region of the second active layer. The one of the source contact region or the drain contact region of the first active layer and the one of the source contact region or the drain contact region of the second active layer overlap each other, and are electrically connected through a via in the first insulating layer and the first connection portion.

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N th frame cycle.

A display panel and a display apparatus are described. In an embodiment, the display panel includes a substrate and a sub-pixel group located at a side of the substrate. In an embodiment, the sub-pixel group includes sub-pixels of at least two different colors and a light-limiting structure. In an embodiment, the sub-pixels share one light-emitting element. In an embodiment, along a direction perpendicular to the substrate, the light-limiting structure overlaps with the light-emitting element and is located at a light exit side of the light-emitting element. In an embodiment, when the display panel displays an image, the sub-pixels in the sub-pixel group are enabled in sequence. In an embodiment, the when one of the sub-pixels is enabled, the light-limiting structure causes light emitted by the light-emitting element to exit only from the enabled sub-pixel.

A display panel and a display device are provided. The display panel includes a plurality of data lines and a plurality of scan lines. An extending direction of the plurality of data lines intersects an extending direction of the plurality of scan lines. The plurality of scan lines includes at least one first scan line. The first scan line includes a first portion. Metal conductivity of the first portion is greater than or equal to metal conductivity of the plurality of data lines.

Provided an array substrate, as well as a method for preparing an array substrate, a display panel, and a display device, includes: substrate; driver circuits located on side of the substrate; signal lead-out structure located on side of the driver circuits facing away from the substrate and including insulating boss and signal lead-out wires one of which electrically connected to an output electrode of a driver circuit, and at least part of the signal lead-out wire extends along sidewall of the insulating boss; a color-resist layer located on side of the driver circuits facing away from the substrate and surrounding sidewall of the signal lead-out structure, and thickness of the color-resist layer less than or equal to extension length of the signal lead-out wire; and a first electrode located on side of the signal lead-out structure facing away from the substrate and electrically connected to the signal lead-out wire.

Provided are display panels and display apparatus. The display panel includes a driving array layer including a pixel circuit and a driving circuit configured to provide a control signal to the pixel circuit. The pixel circuit includes first and third transistors. The driving circuit includes second and fourth transistors. The first to fourth transistors include an active layer including silicon, an active layer including oxide semiconductor, an active layer including oxide semiconductor, and an active layer including silicon. The first and the third transistors are switching transistors of the pixel circuit, |W 1 /L 1 -W 4 /L 4 |<|W 2 /L 2 -W 3 /L 3 |; or the first and the third transistors are a driving transistor and a switching transistor of the pixel circuit, respectively, |W 1 /L 1 -W 4 /L 4|>5 *|W 2 /L 2 -W 3 /L 3 |; or the first and third transistors are a switching transistor and a driving transistor of the pixel circuit, respectively, 5 *|W 1 /L 1 -W 4 /L 4 |<|W 2 /L 2 -W 3 /L 3|.

Provided are display panels and display apparatus. The display panel includes a driving array layer including a pixel circuit and a driving circuit configured to provide a control signal to the pixel circuit. The pixel circuit includes a first capacitor and a first transistor including an active layer including silicon. The driving circuit includes a second capacitor and a second transistor including an active layer including oxide semiconductor. In a direction perpendicular to a plane of the display panel, the first capacitor partially overlaps the first transistor, and the second capacitor does not overlap the second transistor; or in a direction perpendicular to a plane of the display panel, an area of a region where the first capacitor overlaps the first transistor is greater than an area of a region where the second capacitor overlaps the second transistor.

Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.