XILINX, INC.

Bi-directional dynamic function exchange (DFX) can include receiving a circuit design for a programmable integrated circuit (IC). The circuit design includes a plurality of DFX partitions coupled by a signal path. The circuit design can be placed using a first plurality of DFX modules for the plurality of DFX partitions, in part, by selecting a flip-flop of a connection block as a boundary flip-flop of the signal path for each DFX module of the plurality of DFX modules. The circuit design including the signal path can be routed through the selected flip-flops of the connection blocks using a bi-directional routing resource coupling the plurality of connection blocks. The bi-directional routing resource is used as a partition pin placement constraint (PPLOC) node for DFX.

A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.

Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.

Embodiments herein describe a system including a plurality of network resources providing data transmission between a first end point and a second end point by making a request for a network resource reservation to reserve resources on an end-to-end path during a time frame for the data transmission, selecting a routing table, populating the routing table with a limited number of entries, activating the data transmission at a start time of the time frame to an input port corresponding to the routing table, in response to activating the data transmission, forwarding data based on the entries, and determining an end time of the time frame to deactivate the data transmission from the first end point.

The embodiments herein describe techniques for performing ML compilation using a unified interface that combines different processors in a heterogeneous processing system which allows for intelligent partitioning of a ML model. Unlike prior solutions which rely on user preferences to assign the ML model, the unified interface can violate or break the user preferences when partitioning the ML model. The unified interface can receive information from the processors (e.g., a NPU, CPU, GPU, etc.) and determine the capabilities, current workload, power metrics, subgraphs of the ML model they can execute, and the like. With this information, the unified interface can intelligently choose when to violate or break the user-entered priority based instructions.

Machine learning (ML) tools for analyzing semiconductor yield analysis data, such as to infer information related to defects based on feature values of the yield diagnostic data, where the yield diagnostic data includes wafer-level test data, wafer-region based defect densities (DDs), and functional circuit block-based DDs. The wafer region based DDs are a function of numbers of defects within regions of the wafers and physical areas of the regions. The functional circuit block based DDs are a function of numbers of defects of functional circuit blocks and physical areas of the functional circuit blocks. The ML tools may include a supervised learning-based classification model, such as a gradient boosting classifier, an unsupervised outlier detection model, such as a hierarchical density-based spatial clustering of applications with noise model, an unsupervised clustering model, and/or an unsupervised associative model.

Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

Optimizing timing margins across conditions is described. In one or more implementations, a computing system may include an interface circuitry configured to adjust a timing alignment of first and second signals between a central processing unit (CPU) of the system and a device coupled with the CPU and to measure and store one or more margins between the timing alignment and misalignments of the first and second signals. The interface circuitry may be configured to measure and store the timing margins at first and second conditions. The first and second conditions may be different voltages, temperatures, etc. The system may be configured to force the first and/or second condition. The system may be configured to calculate a coefficient from differences in between the margins and between the first and second conditions.

A method includes allocating, at least one boot image, and parsing programs comprising one or more operators. The method further includes determining a count corresponding to each operator included in each program and an estimated program memory consumption of each operator. The count corresponds to each operator and indicates a quantity of times each operator in each program is detected. The at least one boot image is populated with common operators based on a program memory size limit of an hardware accelerator circuitry of an IC device and an estimated program memory consumption of each common operator. The common operators are operators that are within a threshold count. The at least one boot image is populated with non-common operators based on the program memory size limit and an estimated program memory consumption of each non-common operator. The non-common operators are operators that are not within the threshold count.