XINTEC INC.

A chip package includes a semiconductor stack structure, a first redistribution layer, and a molding compound. The semiconductor stack structure includes a first chip having a conductive pad. The first redistribution layer is located on the surface of the first chip and electrically connected to the conductive pad. The molding compound surrounds the semiconductor stack structure and completely covers the external sidewall of the first chip. The width and the thickness of the molding compound are respectively greater than the width and the thickness of the entire semiconductor stack structure. The molding compound has a surface coplanar with the semiconductor stack structure, and said surface of the molding compound is exposed.

A chip package includes a semiconductor substrate, a bonding adhesive, a support element, a first protection layer, and a second protection layer. The top surface of the semiconductor substrate has a conductive pad and a sensing area, and the corner of the top surface of the semiconductor substrate has a groove. The bonding adhesive is located in the groove. The support element covers the bonding adhesive and the conductive pad, and surrounds the sensing area. The first protection layer is located on the bottom surface of the semiconductor substrate. The second protection layer covers the first protection layer, the sidewall of the semiconductor substrate, and the lateral surface of the bonding adhesive.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.

A chip package includes a semiconductor substrate, an isolation layer, a redistribution layer, a first protection layer, a conductive structure, and a second protection layer. The isolation layer is located on a surface of the semiconductor substrate. The redistribution layer is located on the isolation layer and extends to a conductive pad in a through hole. The first protection layer is located on the redistribution layer and the isolation layer, and a portion of the first protection layer is located in the through hole. The conductive structure is located on the redistribution layer. The second protection layer covers the first protection layer, the isolation layer, and the outer sidewall of the semiconductor substrate. The material of the second protection layer is different from the material of the first protection layer, and the second protection layer surrounds and is in contact with the conductive structure.

A leakage detecting assembly includes a sheet leakage detecting module, a signal output unit, and a monitoring control system. The sheet leakage detecting module covers a wielding area or a connection area of a pipeline, and surrounds the pipeline. The sheet leakage detecting module is in direct contact with an outer surface of the pipeline. The signal output unit is electrically connected to the sheet leakage detecting module. The monitoring control system is electrically connected to the signal output unit.

A chip package is provided. The chip package includes a device substrate, a metallization layer, a first redistribution layer (RDL), a passivation layer structure, and an etch stop layer. The metallization layer and the first redistribution layer are respectively disposed on the front-side surface and the backside surface of the device substrate. The passivation layer structure covers the edge surface surrounding the device substrate. The passivation layer structure extends onto the backside surface and covers the first RDL. The etch stop layer is disposed in the metallization layer. The etch stop layer is aligned with the passivation layer structure covering the edge surface, so as to surround the device substrate.

A chip package is provided. The chip package includes a first semiconductor chip, a second semiconductor chip, a first encapsulating layer, a second encapsulating layer, a first through-via, and a second through-via. The second semiconductor chip is stacked on the first semiconductor chip, and the first encapsulating layer and the second encapsulating layer surround the first semiconductor chip and the second semiconductor chip, respectively. In addition, the first through-via and the second through-via penetrate the first encapsulating layer and the second encapsulating layer, respectively, and the second through-via is electrically connected between the second semiconductor chip and the first through-via. A method for forming the chip package are also provided.

A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

A semiconductor device structure is provided. The semiconductor device structure includes a first transparent substrate, a conductive layer, an insulating protective layer, a second transparent substrate, a device substrate, and a bonding layer. The first transparent substrate has a first surface and an opposite second surface. The conductive layer is disposed on the second surface of the first transparent substrate. The insulating protective layer covers the conductive layer and the first transparent substrate. The second transparent substrate is disposed above the first transparent substrate, and has a first surface facing the first transparent substrate and an opposite second surface. The device substrate is disposed on the second surface of the second transparent substrate. The bonding layer is bonded to the insulating protective layer and the first surface of the second transparent substrate.