Akeana, Inc.

An accelerator is accessed. The accelerator includes a systolic array of tiles that include a plurality of rows and a plurality of columns. Each tile in the systolic array of tiles includes one or more multiply-add units. The accelerator includes a row tail associated with each row within the plurality of rows. A first matrix is multiplied by a second matrix in the systolic array. The multiplying is based on a plurality of partial products. A row within the plurality of rows of the systolic array produces one or more partial products within the plurality of partial products. A last tile within the row forwards the one or more partial products to an associated row tail. The one or more partial products that were forwarded are accumulated with one or more previous partial products associated with the row by the associated row tail.

Techniques for coherency management based on coherent hierarchical cache line tracking are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a local cache. A hierarchical cache is coupled to the plurality of processor cores. The hierarchical cache is shared among the plurality of processor cores. Coherency between the plurality of processor cores and the hierarchical cache is managed by a compute coherency block (CCB). A cache line directory is provided for the CCB. The cache line directory includes a core list field and a cache line present field. A cache line operation is detected. The cache line operation is detected by the CCB. The cache line operation is represented by an entry in the cache line directory. The cache line operation is performed, based on corresponding values of the core list field and the line present field.

A processor core is accessed. The processor core is coupled to a memory hierarchy. The processor core is configured to execute shadow stack operations and micro-operations. A shadow stack operation is decoded. The shadow stack operation is associated with a shadow stack pointer (SSP). The shadow stack operation is associated with an implementation mode. The shadow stack operation is substituted with at least two micro-operations. The substituting is based on the implementation mode. The at least two micro-operations are then executed. The shadow stack operation includes an SSP push operation. A first micro-operation within the at least two micro-operations includes a store micro-operation. A store address of the store micro-operation implicitly comprises the SSP. An illegal instruction exception is triggered when an operand of the SSP push operation is not one or more specified integer registers.

Techniques for sharing processor data within a network are disclosed. A system-on-a-chip (SOC) is accessed. The SOC includes a network-on-a-chip (NOC), which comprises an M×N mesh topology. The mesh includes a coherent tile at each mesh point. Each tile includes local snoop vectors (LSVs). A first coherent tile initiates a snoop operation. The tile generates a snoop vector that indicates other tiles to be notified of the snoop operation. The first coherent tile creates directional snoop vectors (DSVs). The creating logically combines the snoop vector with each of the LSVs. A coherent tile adjacent to the first coherent tile is selected. The adjacent tile is located in a cardinal direction from the first tile. A first DSV is chosen based on the cardinal direction. The first tile sends the snoop operation and the chosen first DSV to the selected adjacent tile.

Disclosed embodiments provide techniques for improved performance in processing vector instructions. A processor core is accessed. The processor core is coupled to a memory hierarchy, and the processor core includes one or more vector execution units (VUs), and one or more load store units (LSUs). The processor core includes a vector register file (VRF). The VRF includes multiple vector registers, and each vector register includes multiple vector elements. Vector elements that have a source or destination in contiguous memory are identified. Load store units (LSUs) take advantage of the contiguous memory condition by executing a vector load or vector store operation as a single memory access, requiring a reduced number of clock cycles. The single memory access satisfies each memory operation for each vector element within the vector register file.

Techniques for cache management based on cache management using memory queues are disclosed. A plurality of processor cores is accessed. The plurality of processor cores comprises a coherency domain. Two or more processor cores within the plurality of processor cores generate read operations for a common memory structure coupled to the plurality of processor cores. Coherency for the coherency domain is managed using a compute coherency block (CCB). The CCB includes a memory queue for controlling transfer of cache lines determined by the CCB. The memory queue includes an evict queue and a miss queue. Snoop requests are generated by the CCB. The snoop requests correspond to entries in the memory queue. Cache lines are transferred between the CCB and a bus interface unit. The transferring is controlled by the memory queue. The bus interface unit controls memory accesses.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector floating-point instructions and micro-operations. A vector floating-point instruction is decoded. The decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs). A reorder buffer assigns a reorder buffer ID (ROBID) to each of the one or more VFPMs, in which the assigning includes a micro-sequencer ID (MSID). The processor core executes the one or more VFPMs. The executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag. The architectural floating-point flag is set, based on the first update. The setting occurs after the one or more VFPMs have been committed by the processor core. A temporary floating-point flag is revised. The revising is based on the first update.

A system-on-chip (SoC) is accessed. The SoC includes a mesh network and one or more coherency ordering agents (COAs). The COAs coordinate coherency for one or more processors coupled to the mesh network. The COAs are coupled to one or more communication converters (CCs) by the mesh network. A processor sends a request to a target device. The request is based on a first communications protocol and includes a memory address. The request is sent by a COA to a CC. A request queue within the CC stores the request. The request is checked against one or more additional requests. The CC translates the request, resulting in a converted request, based on a second communications protocol. The translating is based on the checking. The CC transmits the converted request to the target device.

Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Disclosed embodiments provide techniques for communication. A system-on-a-chip (SoC) is accessed. The SoC includes a mesh network that includes a plurality of nodes. At least one node within the plurality of nodes includes a quality-of-service (QoS) agent. Network traffic data is collected by a first QoS agent within a first node. The network traffic data is associated with the first node and the traffic occurs during a first timing window. The first QoS agent receives a request by a primary device within the first node to send data to a secondary device in a second node. The first QoS agent analyzes the network traffic data. A first routing agent within the first node selects an intermediate node within the plurality of nodes, based on the analyzing. The primary device sends the data to the intermediate node.