Akeana, Inc.

Disclosed techniques enable processors that are capable of performing a wide range of vector operations. A processor can support multiple types of instructions. The instructions can include one or more operands, and the one or more operands can include different data types. An A-type instruction can have dependencies on a B-type instruction. An A-type instruction includes a vector instruction. A B-type instruction includes an integer instruction or a floating-point instruction. A datapath is provided to enable intermediate results from a B-type instruction to be supplied to the A-type instruction on which it depends, without utilizing register file resources, such as general-purpose register (GPR) register resources. Vector instruction performance is thereby enabled without the additional resources used with GPR register access.

Disclosed embodiments provide techniques for prefetching. A processor core that executes instructions out of order (OOO) is accessed. The processor core includes a local cache hierarchy, data prefetch logic, and a prefetch table and is coupled to an external memory system. A first load instruction with a first address is detected and causes a miss in the local cache hierarchy. Information pertaining to the first load instruction is saved in an entry of the prefetch table. The information includes the first address, a confidence count, and an out-of-order mask. A second load instruction with a second address is identified. The information is updated based on the detecting. The information is advanced. The second address is the next sequential address after the first address. The advancing is based on the detecting. One or more data prefetch instructions are issued to the second address plus an offset.

Techniques for address translation are disclosed. A processor core is accessed. The processor core includes a memory management unit (MMU) and a unified translation lookaside buffer (TLB) within the MMU. The TLB is configured to support a plurality of page sizes, and the processor core is coupled to an external memory system. The TLB receives a lookup request for a virtual memory address, wherein the virtual memory address corresponds to a process running on the processor core. The TLB accesses a linked list that comprises a page size priority order for the plurality of page sizes. A lookup is performed in the TLB on the virtual memory address, and the lookup is conducted in the page size priority order. The linked list is updated, the updating moves a page size associated with the lookup to a location in the linked list, and a physical address is returned.

Techniques for data sharing are disclosed. A system-on-a-chip (SoC) is accessed. The SoC includes one or more cache coherency blocks (CCBs) and one or more coherency ordering agents (COAs). Each COA includes a directory snoop filter (DSF). Each CCB is communicatively coupled to each COA by a network-on-a-chip (NOC) interface. A CCB requests a cache line associated with a memory address. The CCB is not a sharer of the cache line. A directory snoop filter (DSF) within a COA is read. The reading reveals one or more CCB sharers of the cache line and indicates there is no CCB owner. The COA includes a coherent last level cache (LLC) that contains a valid copy of the cache line. The COA assigns ownership of the cache line to the CCB. The assigning is recorded in the DSF. The cache line is forwarded by the coherent LLC to the CCB.

Techniques for managing computer processors that implement speculative reads are disclosed. A circular queue is accessed. The circular queue comprises a plurality of entries and includes a head pointer and a tail pointer. The head pointer and the tail pointer move independently in a single direction within the circular queue. A software agent selects a read entry associated with a read index within the circular queue. A validity of the read entry is interpreted based on a head wrap bit, a tail wrap bit, a read index, a head index, and a tail index. The circular queue returns an invalid signal to the software agent. The read entry is not modified when the read entry is interpreted as invalid. The circular queue sends data within the read entry to the software agent. The head wrap bit is calculated to be equal to the tail wrap bit.

Techniques for instruction execution, in a processor supporting vector operations, are disclosed. A processor core is accessed. The processor core supports vector operations and is configured to execute micro-operations. A vector load operation is issued. It includes a first number of vector elements, which is determined by a vector length control (VL) register. The vector load operation is split into a series of micro-operations, in which each micro-operation corresponds to a unique vector element and is assigned an element order value. The micro-operations are executed out of order. At least one fault is detected. An earliest faulting micro-operation is determined, based on the element order value of each of the micro-operations. The VL register is updated, based on the earliest faulting micro-operation. All micro-operations that were assigned an element order value higher than an element order value that was assigned to the earliest faulting micro-operation are cancelled.

A processor core is accessed. The processor core includes a direct next program counter cache (DNPC) that includes multiple entries. The processor core executes a branch instruction associated with a program counter (PC) address. An entry within the DNPC that matches a tag associated with the PC address is found. An indirect bit within the matching entry is read. In cases where the indirect bit is not set, a branch target address for the branch instruction is produced by the DNPC. The DNPC generates a prediction for the branch instruction. The prediction is based on a local history register within the entry of the DNPC that matched the tag. A next PC address is determined, based on the branch target address that was produced and the prediction that was generated. The DNPC includes a plurality of prediction tables. Each prediction table is associated with each entry within the DNPC.

Techniques for vector instruction operation are disclosed. A processor core is accessed. The processor core supports vector operations, the processor core includes an execution pipeline, and the execution pipeline is configured to execute micro-operations. A vector operation is issued, in the processor core. The vector operation necessitates a plurality of execution cycles. The vector operation is split into a series of micro-operations. Execution of the series of micro-operations is initiated. An operation exception is received by the processor core. The operation exception is processed. Execution of the series of micro-operations is completed, based on the timing of the operation exception. The splitting, the initiating, and the completing are performed by a micro-operation sequencer within a decode unit of the processor core. The micro-operation sequencer assigns the series of micro-operations, based on a type of the vector operation.

Techniques for processor management are disclosed. One or more processors are accessed. The one or more processors include one or more logical partitions. A processor from the one or more processors executes one or more instructions out of order. The processor detects a deadlock condition. The deadlock condition prevents the one or more instructions from completing. The deadlock condition occurs in a logical partition within the one or more logical partitions. A parallelism of execution in the logical partition is reduced. The reducing allows the one or more instructions to complete. The reducing is based on one or more control bits. Cessation of the deadlock condition is recognized. The parallelism of execution in the logical partition is restored. The restoring is based on the one or more control bits. The one or more instructions execute on one or more threads running on the processor.

Techniques for maintaining cache coherency while sharing data among multiple processors are disclosed. Multiple coherent elements are arranged in an M×N mesh topology. An element can include a compute coherency block (CCB), and a coherency ordering agent (COA). The COAs include a directory snoop filter (DSF), an eviction content addressable memory (eCAM), a miss and snoop queue (MSQ), and a pipeline logic. The CCB and COA include functions for interfacing with a hierarchical cache and directory snoop filter (DSF). A CCB from within one of the multiple coherent elements issues a read request. The corresponding directory snoop filter (DSF) is inspected to determine if there is a slot (way) available for storing information pertaining to the read request. In the event that no eligible vacancies are present in the DSF, a multi-pass process for handling a capacity limit in a DSF is performed.