Amlogic (Shanghai) Co., Ltd.

A method for calibrating crystal frequency offset through a radio frequency signal includes, in Step S1, a radio frequency port of a device is connected to one end of a radio frequency cable through a copper pipe connector and the other end of the radio frequency cable is connected to a Wireless Local Area Network (WLAN) tester which is connected with a control terminal. In Step S2, a user controls the WLAN tester to test the radio frequency signal of the device through the control terminal to obtain a test result, and determines whether a deviation of the radio frequency signal is qualified. If it is qualified, the user exits the test, otherwise the user regulates the crystal circuit of the device under test, and returns to Step S2. The method may not be affected by a probe, thus the measurement may be more accurate.

The PWM waveform generation device comprises a time-division multiplexing module, wherein the time-division multiplexing module is configured for receiving a first preprocessing signal and a second preprocessing signal output by two system clock sources, performing a first time-division processing on the first preprocessing signal to obtain a first time-division signal, and performing a second time-division processing on the second preprocessing signal to obtain a second time-division signal according to a preset strategy, performing multiplexing processing on the first time-division signal and the second time-division signal to obtain a PWM output signal, wherein an output frequency of the PWM output signal is a default standard clock frequency. The present invention has the advantages that the cycle length of one cycle of a PWM waveform depends on cycles of two preprocessing waveforms and the number of the cycles, such that the output waveform frequency may be calibrated to a desired frequency.

The invention relates to a data edge jumping method, applied to a memory system, wherein the memory system comprises a processor and a memory driven by the processor, and a plurality of groups of data lines are connected between the processor and the memory. The data edge jumping method comprising: coding data output by the processor to enable total current produced by data transmission through each of the plurality of groups of data lines at the same time to be zero; transmitting the coded data through the plurality of groups of data cables, and decoding the data before reaching the memory; and inputting the decoded data into the memory, and enabling the total current produced in the data lines to be close to 0 A, so that electromagnetic interference is hardly produced by signals transmitted through the data lines, and allowance of signal radiation is large enough.

A frequency demultiplication adjustment method of PLL comprises obtaining a plurality of corresponding frequency demultiplication frequency points according to a default frequency demultiplication value of a phase-locked loop; obtaining a load state of the processor within a predetermined sampling period, and obtaining a target frequency point of the processor by the processor frequency adjustor; determining a frequency range of a virtual frequency point to be added according to the position of the target frequency point; performing calculation within the frequency range to obtain equivalent frequencies corresponding to virtual frequency points; judging whether the frequency of the target frequency point is equal to the equivalent frequency corresponding to the virtual frequency points; if not, switching the processor frequency adjustor to the corresponding frequency demultiplication frequency point; and adjusting the frequency demultiplication value of the phase-locked loop which outputs a clock source signal corresponding to the virtual frequency points to the processor.